Datenblatt-Suchmaschine für elektronische Bauteile |
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TSB11LV01PT Datenblatt(PDF) 6 Page - Texas Instruments |
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TSB11LV01PT Datenblatt(HTML) 6 Page - Texas Instruments |
6 / 21 page TSB11LV01 3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER SLLS232B – MARCH 1996 – REVISED MAY 1997 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL I/O TYPE DESCRIPTION NAME NO. I/O TYPE DESCRIPTION AGND 21, 23, 24, 26, 27 – Supply Analog circuit ground. The AGND terminals should be tied to the low-im- pedance circuit board ground plane. AVCC 22, 28, 29, 44 – Supply Analog circuit power. AVCC supplies power to the analog portion of the device. It is recommended that a combination of high-frequency decoupling capacitors be connected to AVCC (i.e., paralleled 0.1 µF and 0.001 µF). Lower frequency 10- µF filtering capacitors can also be used. These supply pins are separated internally in the device to provide noise isolation. These terminals should also be tied at a low-impedance point on the circuit board. Individual filtering networks for each is desired. C/LKON 3 I/O CMOS Bus manager capable (input). When set as an input, C/LKON is used to specify in the Self-ID packet that the node is bus manager capable. Link-on (output). When set as an output, C/LKON indicates the reception of a link-on message by asserting a 6.114-MHz signal. The bit value program- ming is done by tying the terminal through a 10-k Ω resistor to VCC (high) or to GND (low). Using either the pullup or pulldown resistor allows the LKON output to override the input value when necessary. CNA 1 O CMOS Cable not active. CNA is asserted high when the TSB11LV01 port is not connected to another active port. CPS 30 I CMOS Cable power status. CPS is normally connected to the cable power through a 400-k Ω resistor. This circuit drives an internal comparator that detects the presence of cable power. This information is maintained in two internal registers and is available to the link by way of a register read. See the Phy- Link Interface Application Note in the IEEE 1394-1995 standard. CTL0, CTL1 8, 9 I/O CMOS Control I/O. The CTL terminals are bidirectional communications control signals between the TSB11LV01 and the link. These signals control the passage of information between the two devices. D0, D1 10, 11 I/O CMOS Data I/O. The D terminals are bidirectional and pass data between the TSB11LV01 and the link. DGND 13, 15, 17, 19, 20, – Supply Digital circuit ground. The DGND terminals should be tied to the low-imped- ance circuit board ground plane. DVCC 14, 18, 45 – Supply Digital circuit power. DVCC supplies power to the digital portion of the de- vice. It is recommended that a combination of high-frequency decoupling capacitors be connected to DVCC (i.e., paralleled 0.1 µF and 0.001 µF). Lower frequency 10- µF filtering capacitors can also be used. These supply pins are separated internally in the device to provide noise isolation. These terminals should also be tied at a low-impedance point on the circuit board. Individual filtering networks for each is desired. BIAS–5V 16 – Supply 5 V bias. BIAS-5V should be connected to the link VCC supply when a 5-V link is connected to the phy. When a 3-V link is used, BIAS-5V should be connected to the phy DVCC. LPS 2 I CMOS Link power status. This terminal is connected to either the VCC supplying the link or to a pulsed output that is active when the link is powered for the purpose of monitoring the link’s power status. When this input is low for more than 2.56 µs, then the link is considered powered down. When this input is high for more than 80 ns, then the link is considered powered up. If the link is not powered, the phy–link interface is disabled, and the TSB11LV01 performs only the basic repeater functions required for network initialization and operation. LREQ 7 I CMOS Link request. LREQ is an input from the link that signals the TSB11LV01 of a request to perform some service. |
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