TSB12LV21B

(PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER

SLLS306– JULY 1998

5

POST OFFICE BOX 655303

Table 1. Signals Sorted by Pin Number (Continued)

PIN NO.

SIGNAL NAME

PIN NO.

SIGNAL NAME

PIN NO.

SIGNAL NAME

PIN NO.

SIGNAL NAME

165

3.3V VCC

168

GND

171

pci_ad29

174

pci_ad27

166

pci_inta

169

pci_ad31

172

3.3V VCC

175

GND

167

pci_req

170

pci_ad30

173

pci_ad28

176

pci_ad26

Terminal Functions

power supply terminals

TERMINAL

I/O

FUNCTION

NAME

NO.

I/O

TYPE

FUNCTION

GND

6, 14, 21, 28, 35, 45,

51, 65, 72, 79, 89,

95, 102, 114, 121,

130, 141, 150, 155,

160, 168, 175

I

Device ground terminals

3.3V VCC

1, 8, 19, 26, 33, 42,

49, 56, 70, 75, 86,

93, 100, 107, 116,

128, 136, 138, 145,

157, 165, 172

I

3.3-V power supply terminal for core logic

5.0V VCC

12, 40, 60, 63, 84,

109, 162

I

5-V power rail for 5-V tolerant Input buffers

PCI system terminals

TERMINAL

I/O

FUNCTION

NAME

NO.

I/O

TYPE

FUNCTION

pci_clk

161

I

System PCI bus clock. This signal ranges from 0MHz–-33MHz MHz and provides timing for all transactions

on the PCI bus. All PCI signals are sampled at the rising edge of PCLK.

pci_reset

163

I

pci_reset. When the PCI bus reset is asserted the pci_reset signal causes the PCILynx-2 to 3-state all

output buffers and reset all internal registers. When pci_reset is asserted, the device is completely

nonfunctional. After pci_reset is deasserted, the PCILynx-2 is in its default state.

pci_inta

166

OD

PCI system interrupt A. This is an open drain signal.