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TSB12LV41A Datenblatt(PDF) 10 Page - Texas Instruments

Teilenummer TSB12LV41A
Bauteilbeschribung  IEEE 1394-1995 Link-Layer Controller for Consumer Applications
Download  199 Pages
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Hersteller  TI [Texas Instruments]
Direct Link  http://www.ti.com
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TSB12LV41A Datenblatt(HTML) 10 Page - Texas Instruments

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List of Illustrations (continued)
Figure
Title
Page
3–30 Snoop Format
3–39
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–31 Cyclemark Format
3–40
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–32 Phy Configuration Format
3–40
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–33 Receive Self-ID Format for Broadcast Write Receive FIFO
3–41
. . . . . . . . . . . . . . . . . .
3–34 Receive Self-ID Format for Bulky Asynchronous Receive FIFO
3–41
. . . . . . . . . . . . . .
3–35 Phy Self-ID Packet #0 Format
3–42
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–36 Phy Self-ID Packet #1, Packet #2, and Packet #3 Format
3–43
. . . . . . . . . . . . . . . . . . .
4–1
TSB12LV41A System Application Diagram
4–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–2
Bulky Data Interface
4–2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–3
BDIF Control Register
4–4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–4
Bulky Data Interface Mode A Typical Application
4–7
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–5
Bulky Data Interface Mode B Typical Application
4–8
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–6
Bulky Data Interface Mode C Typical Application
4–9
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–7
Bulky Data Interface Mode D Typical Application
4–10
. . . . . . . . . . . . . . . . . . . . . . . . . . .
4–8
Functional Timing for Write Operations in the Unidirectional Modes
4–11
. . . . . . . . . . .
4–9
Critical Timing for Write Operations in Unidirectional Mode
4–12
. . . . . . . . . . . . . . . . . .
4–10 Functional Timing for Write Operations in the Asynchronous Mode
4–12
. . . . . . . . . . .
4–11 Functional Timing for Read Operations in Unidirectional Mode
4–13
. . . . . . . . . . . . . . .
4–12 Read from Bulky Interface Unidirectional Mode
4–13
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–13 Functional Timing for Read Operations in Asynchronous Mode
4–14
. . . . . . . . . . . . . . .
4–14 Functional Timing for Write Operations in Bidirectional Mode
4–15
. . . . . . . . . . . . . . . .
4–15 Critical Timing for Write Operations in Bidirectional Mode
4–15
. . . . . . . . . . . . . . . . . . . .
4–16 Functional Timing for Read Operations in Bidirectional Mode
4–16
. . . . . . . . . . . . . . . .
4–17 Critical Timing for Read Operations in Bidirectional Mode
4–17
. . . . . . . . . . . . . . . . . . .
4–18 Functional Timing for Read/Write Interleave Operations in Bidirectional Mode
4–18
. .
4–19 MPEG2Lynx Connections for 68000 Microcontroller
4–20
. . . . . . . . . . . . . . . . . . . . . . . .
4–20 MPEG2Lynx Connections for 8051 Microcontroller
4–21
. . . . . . . . . . . . . . . . . . . . . . . . .
4–21 MPEG2Lynx Connections for TMS320AV7100 ARM Processor
4–21
. . . . . . . . . . . . . .
4–22 TSB12LV41A IOCR Register
4–22
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–23 TMS320AV7100 ARM Read/Write Critial Timing
4–26
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–24 TMS320AV7100 Handshake Mode Read Timing
4–27
. . . . . . . . . . . . . . . . . . . . . . . . . . .
4–25 TMS320AV7100 Handshake Mode Write Timing
4–27
. . . . . . . . . . . . . . . . . . . . . . . . . . .
4–26 TMS320AV7100 ARM Blind Access Mode Read Timing
4–28
. . . . . . . . . . . . . . . . . . . . .
4–27 TMS320AV7100 ARM Blind Access Mode Write Timing
4–28
. . . . . . . . . . . . . . . . . . . . .
4–28 Motorola 68000 Read Critical Timing
4–31
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–29 Motorola 68000 Write Critical Timing
4–32
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–30 Motorola 68000 Read Timing
4–33
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–31 Motorola 68000 Write Timing
4–33
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–32 Intel 8051 Read Critial Timing
4–35
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–33 Intel 8051 Write Critial Timing
4–36
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–34 Intel 8051 Read Timing (Blind Access Read)
4–37
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–35 Intel 8051 Write Timing (Blind Access Write)
4–37
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–36 Big Endian Illustration chart
4–39
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–37 Little Endian Illustration chart
4–39
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


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