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TSB12LV32IPZ Datenblatt(PDF) 3 Page - Texas Instruments

Teilenummer TSB12LV32IPZ
Bauteilbeschribung  IEEE 1394-1995 and P1394a Compliant General-Purpose Link-Layer Controller
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Hersteller  TI [Texas Instruments]
Direct Link  http://www.ti.com
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TSB12LV32IPZ Datenblatt(HTML) 3 Page - Texas Instruments

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Contents
Section
Title
Page
1
Overview
1–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
TSB12LV32 Description
1–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
TSB12LV32 Features
1–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
Functional Block Diagram
1–2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4
Terminal Assignments
1–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5
Terminal Functions
1–4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.1 STAT0, STAT1, and STAT2 Programming
1–7
. . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Internal Registers
2–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
TSB12LV32 Configuration Registers
2–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
Configuration Register Definitions
2–4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1 Version Register at 00h
2–4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2 Data Mover Control Register at 04h
2–4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3 Control Register at 08h
2–6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.4 Interrupt/Interrupt Mask Register at 0Ch and 10h
2–9
. . . . . . . . . . . . . . . . . . . . .
2.2.5 Cycle Timer Register at 14h
2–11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.6 Isochronous Port Register at 18h
2–12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.7 Maint_Control Register at 1Ch
2–13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.8 Diagnostic Register at 20h
2–14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.9 Phy Access Register at 24h
2–15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.10 Reserved Registers at 28h – 2Ch
2–15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.11 FIFO Status Register at 30h
2–16
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.12 Bus Reset Register at 34h
2–17
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.13 Header0 Register at 38h
2–18
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.14 Header1 Register at 3Ch
2–19
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.15 Header2 Register at 40h
2–19
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.16 Header3 Register at 44h
2–19
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.17 Trailer Register at 48h
2–20
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.18 Asynchronous Retry Register at 4Ch
2–21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.19 Asynchronous Retry Register at 4Ch
2–21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
Microcontroller Interface
3–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Microcontroller Byte Stack (Write) Operation
3–2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
Microcontroller Byte Unstack (Read)
3–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
Microcontroller Interface Read/Write Timing
3–4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1 Microcontroller Handshake Mode
3–4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2 Microcontroller Fixed-Timing Mode
3–7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.3 Microcontroller ColdFire Mode
3–12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.4 Microcontroller Critical TIming
3–13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.5 Endian Swapping
3–14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
Link Core
4–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
Physical Interface
4–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


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