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TSB14C01AI Datenblatt(PDF) 5 Page - Texas Instruments |
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TSB14C01AI Datenblatt(HTML) 5 Page - Texas Instruments |
5 / 31 page TSB14C01A, TSB14C01AI, TSB14C01AM 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER SGLS107A – FEBRUARY 1999 – REVISED NOVEMBER 1999 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL NAME PM NO. HV NO. TYPE I/O DESCRIPTION ARB_CLK 1 11 TTL O Arbitration clock. ARB_CLK is the clock used for arbitration. ARB_CLK is for test and debug. It can be put into a high-impedance state by PTEST_INDRV. This terminal is not used in normal operation and is always at 49.152 MHz. CTL0, CTL1 13, 14 23, 24 TTL I/O Control I/O. These are bidirectional signals that communicate between the TSB14C01A and the link that controls passage of information between the two devices. D0, D1 15, 16 25, 26 TTL I/O Data I/O. These are bidirectional information signals that communicate between the TSB14C01A and the link layer. ENA_PRI 4 14 TTL I Enable priority. ENA_PRI is tied low to enable the 7-bit bus request. See Table 1 for more information. EN_EXID 18 30 TTL I Enable external ID. When EN_EXID is asserted high, the ID for this node is set externally by EX_ID. When this terminal is tied/driven low, the source of the ID comes from the internal ID register. EN_EXPRI 19 31 TTL I Enable external priority. When EN_EXPRI is asserted high (external priority enabled) the priority level for this node is set externally (see Table 1). This terminal should be tied low when not used. EX_ID5 – EX_ID0 20,21,22, 23,24,25 32,33,34, 35,36,37 TTL I External ID. The ID for this node is determined by the value on the EX_ID terminals. Bit 0 is the MSB. EX_PRI3 – EX_PRI0 27,28, 29,30 39,40, 41,42 TTL I External priority. The priority for this node is determined by the values on the EX_PRI terminals. See Table 1 for more information. GND 7,12,26, 36,38,49, 51,54,60, 64 4,8,17, 22,38,48, 50,61,63, 66 Supply — Circuit ground LREQ 8 18 TTL I Link request input. LREQ is an input from the link used by the link to signal the TSB14C01A of a request to perform some service. VCC 3,5,9,17, 34,41,57, 59,61,62 1,3,5,6, 13,15,19, 29,46,53 Supply — Circuit power NC 31,32,33, 44,45,46, 47,48,53, 56 9,10,27, 28,43–45, 56–60, 65,68 — — Not connected. These terminals must be left floating. N_OEB_D 37 49 TTL O External driver enable. N_OEB_D is a negative active signal that enables the external driver for TDATA and TSTRB. N_POR 6 16 TTL I Logic reset input . Forcing N_POR low causes a reset condition and resets the internal logic to the reset start state. OSC_SEL 50 62 VCC / GND I Select clock frequency. OSC_SEL should be pulled up to VCC when the operating frequency is 50 MHz. When the operating frequency is 100 MHz then it should be pulled to ground. It should not be left floating . PHYENA 2 12 TTL O Phy enable. When the phy is driving it is low, PHYENA is the control to the CTL0, CTL1, D0, and D1 drivers. PHYENA is for test and debug. It can be put into a high-impedance state by PTEST_INDRV. This terminal is not used in normal operation. PTEST_INDRV 35 47 TTL I Test output enable. PTEST_INDRV enables/disables the drivers to the test terminals ARB_CLK, PHYENA, and RPREFIX. During normal operation, PTEST_INDRV should be tied to VCC to disable the drivers. RDATA 43 55 TTL I Receive data. Incoming data is received at the data rate. |
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