TSB41LV03A datasheet(8/50 Pages) TI

Teilenummer	TSB41LV03A

Bauteilbeschribung	IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER

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TSB41LV03A, TSB41LV03AI

IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER

SLLS364A – JULY 1999 – REVISED MAY 2000

8

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

TYPE

NO.

I/O

DESCRIPTION

FILTER0

FILTER1

CMOS

71

72

I/O

PLL filter terminals. These terminals are connected to an external capacitor to form a lag-lead filter

required for stable operation of the internal frequency-multiplier PLL running off of the crystal

oscillator. A 0.1-

µF ± 10% capacitor is the only external component required to complete this filter.

ISO

CMOS

26

I

Link interface isolation control input. This terminal controls the operation of output differentiation

logic on the CTL and D terminals. If an optional isolation barrier of the type described in Annex J of

IEEE Std 1394-1995 is implemented between the TSB41LV03A and LLC, the ISO terminal should

be tied low to enable the differentiation logic. If no isolation barrier is implemented (direct

connection), or TI bus holder isolation is implemented, the ISO terminal should be tied high to disable

the differentiation logic. For additional information refer to TI application note

Serial Bus Galvanic

Isolation, SLLA011.

LPS

CMOS

5 V tol

19

I

Link power status input. This terminal is used to monitor the active/power status of the link layer

controller and to control the state of the PHY-LLC interface. This terminal should be connected to

either the VDD supplying the LLC through a 10 kΩ resistor, or to a pulsed output which is active when

the LLC is powered. A pulsed signal should be used when an isolation barrier exists between the

LLC and PHY.(See Figure 8)

The LPS input is considered inactive if it is sampled low by the PHY for more than 2.6

µs (128

SYSCLK cycles), and is considered active otherwise (i.e., asserted steady high or an oscillating

signal with a low time less than 2.6

µs). The LPS input must be high for at least 21 ns in order to be

guaranteed to be observed as high by the PHY.

When the TSB41LV03A detects that LPS is inactive, it will place the PHY-LLC interface into a

low-power reset state. In the reset state, the CTL and D outputs are held in the logic zero state and

the LREQ input is ignored; however, the SYSCLK output remains active. If the LPS input remains low

for more than 26

µs (1280 SYSCLK cycles), the PHY–LLC interface is put into a low–power disabled

state in which the SYSCLK output is also held inactive. The PHY-LLC interface is placed into the

disabled state upon hardware reset.

The LLC is considered active only if both the LPS input is active and the LCtrl register bit is set to 1,

and is considered inactive if either the LPS input is inactive or the the LCtrl register bit is cleared to 0.

LREQ

CMOS

5 V tol

1

I

LLC Request input. The LLC uses this input to initiate a service request to the TSB41LV03A. Bus

holder is built into this terminal.

PC0

PC1

PC2

CMOS

23

24

25

I

Power class programming inputs. On hardware reset, these inputs set the default value of the power

class indicated during self-ID. Programming is done by tying the terminals high or low. Refer to Table

9 for encoding.

PD

CMOS

5 V tol

18

I

Power-down input. A high on this terminal turns off all internal circuitry except the cable-active

monitor circuits, which control the CNA output. Asserting the PD input high also activates an internal

pull-down on the RESET terminal so as to force a reset of the internal control logic.

PLLGND

Supply

74, 75

–

PLL circuit ground terminals. These terminals should be tied together to the low impedance circuit

board ground plane.

PLLVDD

Supply

73

–

PLL circuit power terminals. A combination of high-frequency decoupling capacitors near each

terminal are suggested, such as paralleled 0.1

µF and 0.001 µF. Lower frequency 10-µF filtering

capacitors are also recommended. These supply terminals are separated from DVDD and AVDD

internal to the device to provide noise isolation. They should be tied at a low-impedance point on the

circuit board.

RESET

CMOS

78

I

Logic reset input. Asserting this terminal low resets the internal logic. An internal pullup resistor to

VDD is provided so only an external delay capacitor in parallel with a resistor are required for proper

power-up operation (see

power-up reset in the APPLICATIONS INFORMATION section). The

RESET terminal also incorporates an internal pulldown which is activated when the PD input is

asserted high. This input is otherwise a standard logic input, and can also be driven by an open-drain

type driver.

R0

R1

Bias

66

67

–

Current setting resistor terminals. These terminals are connected to an external resistance to set the

internal operating currents and cable driver output currents. A resistance of 6.3 k

Ω ±1% is required

to meet the IEEE Std 1394-1995 output voltage limits.

SE

CMOS

32

I

Test control input. This input is used in manufacturing test of the TSB41LV03A. For normal use this

terminal should be tied to GND through a 1-k

Ω pulldown resistor.

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