Datenblatt-Suchmaschine für elektronische Bauteile |
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TSC2117 Datenblatt(PDF) 10 Page - Texas Instruments |
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TSC2117 Datenblatt(HTML) 10 Page - Texas Instruments |
10 / 192 page (1) DAC to speaker-out PSRR measurement is calculated as PSRR + 20 log10 VSIG Supp V SPK1 2 . TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller SLAS550A – APRIL 2009 – REVISED JUNE 2009 www.ti.com Electrical Characteristics (continued) At 25 °C, AVDD, HVDD, IOVDD, TSVDD, = 3.3 V, SLVDD, SRVDD = 3.6V, DVDD = 1.8 V, VREF = 3.3 V, f S (audio) = 48 kHz, CODEC_CLKIN = 256 × f S, PLL = Off, SAR input is AUX1, VOL/MICDET pin disabled (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DAC OUTPUT to CLASS-D SPEAKER OUTPUT; Load = 8 Ω (differential), 50 pF (continued) SLVDD = SRVDD = 3.6 V, BTL measurement, DAC THD Total harmonic distortion input = –6 dBFS, DAC VCM (page 1/register 31, bits –72 dB D4–D3) = 1.65 V, class-D gain = 6 dB SLVDD = SRVDD = 3.6 V, BTL measurement, DAC Total harmonic distortion + THD+N input = –6 dBFS, DAC VCM (page 1/register 31, bits –71 dB noise D4–D3) = 1.65 V, class-D gain = 6 dB SLVDD = SRVDD = 3.6 V, BTL measurement, ripple PSRR Power-supply rejection ratio(1) 57 dB on SLVDD/SRVDD = 200 mVp-p at 1 kHz Mute attenuation 110 dB SLVDD = SRVDD = 3.6 V, BTL measurement, DAC VCM (page 1/register 31, bits D4–D3) = 1.65 V, 540 class-D gain = 18 dB, THD = 10% mW SLVDD = SRVDD = 4.3 V, BTL measurement, DAC PO Maximum output power VCM (page 1/register 31, bits D4–D3) = 1.65 V, 790 class-D gain = 18 dB, THD = 10% SLVDD = SRVDD = 5.5 V, BTL measurement, DAC VCM (page 1/register 31, bits D4–D3) = 1.65 V, 1.29 W class-D gain = 18 dB, THD = 10% Output-stage leakage current SLVDD = SRVDD = 4.3 V, device is powered down 80 nA for direct battery connection (power-up-reset condition) ADC and DAC POWER CONSUMPTION For ADC and DAC power consumption based per selected processing block, see Section 5.4 DIGITAL INPUT/OUTPUT Logic CMOS family 0.7 × IIH = 5 µA, IOVDD ≥ 1.6 V IOVDD VIH V IIH = 5 µA, IOVDD < 1.6 V IOVDD 0.3 × IIL = 5 µA, IOVDD ≥ 1.6 V –0.3 IOVDD VIL V Logic level IIL = 5 µA, IOVDD < 1.6 V 0 0.8 × VOH IOH = 2 TTL loads V IOVDD 0.1 × VOL IOL = 2 TTL loads V IOVDD Capacitive load 10 pF ELECTRICAL SPECIFICATIONS 10 Submit Documentation Feedback |
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Ähnliche Beschreibung - TSC2117 |
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