Datenblatt-Suchmaschine für elektronische Bauteile |
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TSC2117IRGZT Datenblatt(PDF) 11 Page - Texas Instruments |
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TSC2117IRGZT Datenblatt(HTML) 11 Page - Texas Instruments |
11 / 192 page 3.4 Timing Characteristics 3.4.1 I 2S/LJF/RJF Timing in Master Mode T0145-06 WCLK BCLK SDOUT SDIN t (DO-BCLK) d t (DO-WS) d t (WS) d t (DI) S t (DI) h t r t f TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller www.ti.com SLAS550A – APRIL 2009 – REVISED JUNE 2009 All specifications at 25 °C, DVDD = 1.8 V Note: All timing specifications are measured at characterization but not tested at final test. PARAMETER IOVDD = 1.1 V IOVDD = 3.3 V UNITS MIN MAX MIN MAX td(WS) WCLK delay 45 20 ns td(DO-WS) WCLK to DOUT delay (for LJF mode only) 45 20 ns td(DO-BCLK) BCLK to DOUT delay 45 20 ns ts(DI) SDIN setup 8 6 ns th(DI) SDIN hold 8 6 ns tr Rise time 25 10 ns tf Fall time 25 10 ns Figure 3-1. I2S/LJF/RJF Timing in Master Mode Submit Documentation Feedback ELECTRICAL SPECIFICATIONS 11 |
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