Datenblatt-Suchmaschine für elektronische Bauteile |
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UC1727 Datenblatt(PDF) 5 Page - Texas Instruments |
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UC1727 Datenblatt(HTML) 5 Page - Texas Instruments |
5 / 7 page UC1727 UC2727 UC3727 APPLICATION INFORMATION (cont.) Figure 4. Rising Edge Waveform Figure 5. Transient Desaturation Response GATE DRIVE WAVEFORM The rising edge of OUT can be programmed for a two step sequence as shown in Figure 4. The plateau voltage is programmed by a resistive divider from VCC to COM applied at CLAMP. CLAMP must be bypassed to COM. The plateau voltage is approximately OUT = CLAMP. The plateau time is set by a resistor from TRC to VCC and a capacitor to COM as: Tp = RC ln R −7.6k R −12.4k . TRC also programs a blanking time during which the chip ignores the desaturation comparator. The blanking time is: Tb = Tp + 0.4RC. In the event that desaturation is detected outside the blanking interval, OUT will be driven back to the CLAMP plateau for a fault time set by a resistor from FRC to VCC and a capacitor to COM as: Tf = RC ln R −7.6k R −12.4k . If the event is transient, OUT will return high at the end of Tf as shown in Figure 5. During Tf, FRPLY is open. After Tf, FRPLY is connected to COM. Desaturation shown in Figure 6 that persists longer than Tf will cause OUT to be driven low. The chip will not ac- cept a command to drive OUT high for a delay period of Td = 0.4RC FRPLY will be open during this entire period. Figure 2. Input Waveform Figure 3. Output Pulsing Caused By Transformer Ringing 5 |
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