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STK12C68-5 Datenblatt(PDF) 10 Page - Cypress Semiconductor

Teilenummer STK12C68-5
Bauteilbeschribung  64 Kbit (8K x 8) AutoStore nvSRAM
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Hersteller  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

STK12C68-5 Datenblatt(HTML) 10 Page - Cypress Semiconductor

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STK12C68-5 (SMD5962-94599)
Document Number: 001-51026 Rev. **
Page 10 of 18
SRAM Write Cycle
Parameter
Description
35 ns
55 ns
Unit
Min
Max
Min
Max
Cypress
Parameter
Alt
tWC
tAVAV
Write Cycle Time
35
55
ns
tPWE
tWLWH, tWLEH
Write Pulse Width
25
45
ns
tSCE
tELWH, tELEH
Chip Enable To End of Write
25
45
ns
tSD
tDVWH, tDVEH
Data Setup to End of Write
12
25
ns
tHD
tWHDX, tEHDX
Data Hold After End of Write
0
0
ns
tAW
tAVWH, tAVEH
Address Setup to End of Write
25
45
ns
tSA
tAVWL, tAVEL
Address Setup to Start of Write
0
0
ns
tHA
tWHAX, tEHAX
Address Hold After End of Write
0
0
ns
tHZWE
[9,10]
tWLQZ
Write Enable to Output Disable
13
15
ns
tLZWE
[9]
tWHQX
Output Active After End of Write
5
5
ns
Switching Waveforms
Figure 10. SRAM Write Cycle 1: WE Controlled [11, 12]
Figure 11. SRAM Write Cycle 2: CE Controlled [11, 12]
tWC
tSCE
tHA
tAW
tSA
tPWE
tSD
tHD
tHZWE
tLZWE
ADDRESS
CE
WE
DATA IN
DATA OUT
DATA VALID
HIGH IMPEDANCE
PREVIOUS DATA
tWC
ADDRESS
tSA
tSCE
tHA
tAW
tPWE
tSD
tHD
CE
WE
DATA IN
DATA OUT
HIGH IMPEDANCE
DATA VALID
Notes
10. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
11. HSB must be high during SRAM Write cycles.
12. CE or WE must be greater than VIH during address transitions.
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