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CS2000P-CZZR Datenblatt(PDF) 3 Page - Cirrus Logic |
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CS2000P-CZZR Datenblatt(HTML) 3 Page - Cirrus Logic |
3 / 30 page CS2000-OTP DS758F1 3 6.3.2 Reference Clock Input Divider (RefClkDiv[1:0]) .................................................................... 24 6.3.3 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 24 6.3.4 Low-Frequency Ratio Configuration (LFRatioCfg) ................................................................ 24 6.3.5 M2 Pin Configuration (M2Config[2:0]) ................................................................................... 25 6.3.6 Clock Input Bandwidth (ClkIn_BW[2:0]) ................................................................................ 25 7. CALCULATING THE USER DEFINED RATIO .................................................................................... 26 7.1 High Resolution 12.20 Format ....................................................................................................... 26 7.2 High Multiplication 20.12 Format ................................................................................................... 26 8. PROGRAMMING INFORMATION ........................................................................................................ 27 9. PACKAGE DIMENSIONS .................................................................................................................... 28 THERMAL CHARACTERISTICS ......................................................................................................... 28 10. ORDERING INFORMATION .............................................................................................................. 29 11. REVISION HISTORY .......................................................................................................................... 30 LIST OF FIGURES Figure 1. Typical Connection Diagram ........................................................................................................ 5 Figure 2. CLK_IN Sinusoidal Jitter Tolerance ............................................................................................. 8 Figure 3. CLK_IN Sinusoidal Jitter Transfer ................................................................................................ 8 Figure 4. CLK_IN Random Jitter Rejection and Tolerance .........................................................................8 Figure 5. Delta-Sigma Fractional-N Frequency Synthesizer .......................................................................9 Figure 6. Hybrid Analog-Digital PLL .......................................................................................................... 10 Figure 7. Fractional-N Source Selection Overview ................................................................................... 10 Figure 8. Internal Timing Reference Clock Divider ................................................................................... 11 Figure 9. REF_CLK Frequency vs a Fixed CLK_OUT .............................................................................. 12 Figure 10. External Component Requirements for Crystal Circuit ............................................................ 12 Figure 11. Low bandwidth and new clock domain .................................................................................... 13 Figure 12. High bandwidth with CLK_IN domain re-use ........................................................................... 13 Figure 13. Ratio Feature Summary ........................................................................................................... 17 Figure 14. PLL Clock Output Options ....................................................................................................... 18 Figure 15. Auxiliary Output Selection ........................................................................................................ 18 Figure 16. M2 Mapping Options ................................................................................................................ 19 Figure 17. Parameter Configuration Sets .................................................................................................. 22 LIST OF TABLES Table 1. Modal and Global Configuration .................................................................................................. 11 Table 2. Ratio Modifier .............................................................................................................................. 15 Table 3. Example 12.20 R-Values ............................................................................................................ 26 Table 4. Example 20.12 R-Values ............................................................................................................ 26 |
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