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CS5566-ISZ Datenblatt(PDF) 10 Page - Cirrus Logic |
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10 / 30 page CS5566 10 DS806PP2 5/4/09 DIGITAL CHARACTERISTICS TA = TMIN to TMAX; VL = 3.3V, ±5% or VL = 2.5V, ±5% or 1.8V, ±5%; VLR = 0V DIGITAL FILTER CHARACTERISTICS TA = TMIN to TMAX; VL = 3.3V, ±5% or VL = 2.5V, ±5% or 1.8V, ±5%; VLR = 0V 16. See Figure 4 to understand conversion timing. The 160 MCLK group delay occurs during the 354 MCLK high-power period of a conversion cycle. See Section 3.2 Power Consumption for more detail. Parameter Symbol Min Typ Max Unit Input Leakage Current Iin -- 2 µA Digital Input Pin Capacitance Cin -3 - pF Digital Output Pin Capacitance Cout -3 - pF MCLK SCLK(i) SDO CS RDY LSB MSB t19 t18 t20 t17 t15 t21 Figure 5. SEC Mode - Discontinuous SCLK Read Timing (Not to Scale) Parameter Symbol Min Typ Max Unit Group Delay (Note 16) - - 160 - MCLKs |
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