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MC-4R128CPE6C-845 Datenblatt(PDF) 11 Page - Elpida Memory

Teilenummer MC-4R128CPE6C-845
Bauteilbeschribung  Direct Rambus??DRAM RIMM??Module 128M-BYTE (64M-WORD x 16-BIT)
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Hersteller  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

MC-4R128CPE6C-845 Datenblatt(HTML) 11 Page - Elpida Memory

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Preliminary Data Sheet E0047N11
11
MC-4R128CPE6C
Timing Parameters
The following timing parameters are from the RDRAMs pins, not the RIMM. Please refer to the RDRAM data sheet
(
µPD488448) for detailed timing diagrams.
Para-
Description
MIN.
MAX.
Units
meter
-845
-745
-653
tRC
Row Cycle time of RDRAM banks - the interval between ROWA packets with
ACT commands to the same bank.
28
28
28
tCYCLE
tRAS
RAS-asserted time of RDRAM bank - the interval between ROWA packet with ACT
command and next ROWR packet with PRER
Note 1 command to the same bank.
20
20
20
Note 2
64
µs
tCYCLE
tRP
Row Precharge time of RDRAM banks - the interval between ROWR packet with
PRER
Note 1 command and next ROWA packet with ACT command to the same
bank.
8
8
8
tCYCLE
tPP
Precharge-to-precharge time of RDRAM device - the interval between
successive ROWR packets with PRER
Note 1 commands to any banks of the
same device.
8
8
8
tCYCLE
tRR
RAS-to-RAS time of RDRAM device - the interval between successive ROWA
packets with ACT commands to any banks of the same device.
8
8
8
tCYCLE
tRCD
RAS-to-CAS Delay - the interval from ROWA packet with ACT command to
COLC packet with RD or WR command. Note - the RAS-to-CAS delay seen
by the RDRAM core (tRCD-C) is equal to tRCD-C = 1 + tRCD because of differences in
the row and column paths through the RDRAM interface.
9
7
7
tCYCLE
tCAC
CAS Access delay - the interval from RD command to Q read data. The
equation for tCAC is given in the TPARM register.
8
8
8
12
tCYCLE
tCWD
CAS Write Delay - interval from WR command to D write data.
6
6
6
6
tCYCLE
tCC
CAS-to-CAS time of RDRAM bank - the interval between successive COLC
commands.
4
4
4
tCYCLE
tPACKET
Length of ROWA, ROWR, COLC, COLM or COLX packet.
4
4
4
4
tCYCLE
tRTR
Interval from COLC packet with WR command to COLC packet which causes
retire, and to COLM packet with bytemask.
8
8
8
tCYCLE
tOFFP
The interval (offset) from COLC packet with RDA command, or from COLC
packet with retire command (after WRA automatic precharge), or from COLC
packet with PREC command, or from COLX packet with PREX command to
the equivalent ROWR packet with PRER. The equation for tOFFP is given in the
TPARM register.
4
4
4
4
tCYCLE
tRDP
Interval from last COLC packet with RD command to ROWR packet with
PRER.
4
4
4
tCYCLE
tRTP
Interval from last COLC packet with automatic retire command to ROWR
packet with PRER.
4
4
4
tCYCLE
Notes 1. Or equivalent PREC or PREX command.
2. This is a constraint imposed by the core, and is therefore in units of ms rather than tCYCLE.


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