Datenblatt-Suchmaschine für elektronische Bauteile |
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DM9000AE Datenblatt(PDF) 10 Page - Davicom Semiconductor, Inc. |
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DM9000AE Datenblatt(HTML) 10 Page - Davicom Semiconductor, Inc. |
10 / 60 page DM9000A Ethernet Controller with General Processor Interface Final 10 Version: DM9000A-17-DS-F01 May 10, 2006 5. Pin Description I = Input O = Output I/O = Input/Output O/D = Open Drain P = Power # = asserted low PD = internal pull-low about 60K 5.1 Processor Interface Pin No. Pin Name Type Description 35 IOR# I,PD Processor Read Command This pin is low active at default, its polarity can be modified by EEPROM setting. See the EEPROM content description for detail 36 IOW# I,PD Processor Write Command This pin is low active at default, its polarity can be modified by EEPROM setting. See the EEPROM content description for detail 37 CS# I,PD Chip Select A default low active signal used to select the DM9000A. Its polarity can be modified by EEPROM setting. See the EEPROM content description for detail. 32 CMD I,PD Command Type When high, the access of this command cycle is DATA port When low, the access of this command cycle is INDEX port 34 INT O,PD Interrupt Request This pin is high active at default, its polarity can be modified by EEPROM setting or by strap pin EECK. See the EEPROM content description for detail 18,17,16, 14,13,12, 11,10 SD0~7 I/O,PD Processor Data Bus bit 0~7 31,29,28, 27,26,25, 24,22 SD8~15 I/O,PD Processor Data Bus bit 8~15 In 16-bit mode, these pins act as the processor data bus bit 8~15; When EECS pin is pulled high , they have other definitions. See 8-bit mode pin description for details. 5.1.1 8-bit mode pins Pin No. Pin Name Type Description 22 WAKE O,PD Issue a wake up signal when wake up event happens 24 LED3 O,PD Full-duplex LED In LED mode 1, Its low output indicates that the internal PHY is operated in full-duplex mode, or it is floating for the half-duplex mode of the internal PHY In LED mode 0, Its low output indicates that the internal PHY is operated in 10M mode, or it is floating for the 100M mode of the internal PHY Note: LED mode is defined in EEPROM setting. 25,26,27 GP6~4 O,PD General Purpose output pins: These pins are output only for general purpose that are configured by register 1Fh. GP6 pin also act as trap pin for the INT output type. When GP6 is pulled high, the INT is Open-Drain output type; Otherwise it is force output type. 28,29,31 GP3,GP2,GP1 I/O General I/O Ports Registers GPCR and GPR can program these pins |
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Ähnliche Beschreibung - DM9000AE |
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