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ES5106 Datenblatt(PDF) 11 Page - Cyrustek corporation

Teilenummer ES5106
Bauteilbeschribung  3 1/2 DIGIT A/D CONVERTER W/LCD
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Hersteller  CYRUSTEK [Cyrustek corporation]
Direct Link  http://www.cyrustek.com.tw
Logo CYRUSTEK - Cyrustek corporation

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ES5106
3 1/2 DIGIT A/D CONVERTER W/LCD
03/05/14
11
System Timing
The oscillator frequency is divided by four prior to clocking the
internal decade counters. The signal integrate takes a fixed 1000
counts time period which is equal to 4000 clock pulses. The back
plane drive signal is derived by dividing clock frequency by 800. To
make a maximum rejection of line frequency (60Hz or 50Hz) noise
pickup, the signal integrate period should be a multiple of the line
frequency period. For 600Hz noise rejection, oscillator frequencies
of 120KHz, 80KHz, 60KHz, 48KHz, 40KHz, etc. should be selected.
For 50Hz rejection, oscillator frequencies of 100KHz, 50KHz,
40KHz, etc. would be suitable.
For all ranges of frequency Rosc should be 100KΩ, Cosc is
selected from the approximate equation f=0.45/RC. For 48KHz
clock (3readings/second), Cosc=100PF.
Integrating Resistor
The input buffer amplifier and integrator both have class A
output stage with 100μA of quiescent current and can supply
20μA drive currents with negligible linearity errors. The integrating
resistor should be chosen to remain in the output stage linear drive
region. It should be noticed that the integrating resistor should not
be so large such that the leakage currents of printed circuit board
will induce errors. For a 200mV full-scale the recommended
integrating resistor value is 47KΩ and for 2V full-scale is 470KΩ.


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