Datenblatt-Suchmaschine für elektronische Bauteile |
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SS812-46CVTR Datenblatt(PDF) 7 Page - Silicon Standard Corp. |
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SS812-46CVTR Datenblatt(HTML) 7 Page - Silicon Standard Corp. |
7 / 8 page www.SiliconStandard.com 7 of 8 SS811, SS812 Rev.1.01 4/06/2004 MANUAL RESET INPUT Many microprocessor-based products require manual reset capability, allowing operators, test technicians, or external logic circuitry to initiate a reset. Logic low on MR asserts reset. Reset will remain asserted for the Reset Active Timeout Period (tRP) after MR returns high. This input has an internal 20K O pull-up resistor, so it can be floating if it is not used. MR can be driven with TTL or CMOS-logic levels, or with open-drain/collector outputs. Another alternative is to connect a normal switch from MR to GND to create a manual reset function. Connecting a 0.1µF capacitor from MR to ground can provide noise immunity to prevent noise caused by long cables of MR or noisy environment. BENEFITS OF HIGHLY ACCURATE RESET THRESHOLD The SS811/812 with specified voltage as 5V ±10% or 3V ±10% are ideal for systems using a 5V±5% or 3V±5% power supply. The reset is guaranteed to assert after the power supply falls out of regulation, but before power drops below the minimum specified operating voltage range of the system ICs. The pre-trimmed thresholds reduce the range over which an undesirable reset may occur. APPLICATION INFORMATION NEGATIVE-GOING VCC TRANSIENTS In addition to issuing a reset to the microprocessor during power-up, power-down, and brownout conditions, the SS811 series are relatively resistant to short-duration negative-going VCC transient. ENSURING A VALID RESET OUTPUT DOWN TO VCC=0 When VCC falls below 0.9V, the SS811 RESET output no longer sinks current; it becomes an open circuit. In this case, high-impedance CMOS logic inputs connected to RESET can drift to undetermined voltages. Therefore, the SS811/2 is perfect for most CMOS applications with VCC down to 0.9V. However in applications where RESET must be valid down to 0V, adding a pull-down resistor to RESET causes any leakage currents to flow to ground, holding RESET low. INTERFACING TO MICROPROCESSORS WITH BIDIRECTIONAL RESET PINS Microprocessors with bidirectional reset pins may have contention with the SS811/812 reset outputs. If the SS811 RESET output is asserted high and the microprocessor wants to pull it low, indeterminate logic levels may occur. To correct such cases, connect a resistor between the SS811 RESET (or SS812 RESET) output and the microprocessor reset I/O. Buffer the reset output to other system components. |
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