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74LVC3G14GD Datenblatt(PDF) 9 Page - NXP Semiconductors |
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74LVC3G14GD Datenblatt(HTML) 9 Page - NXP Semiconductors |
9 / 18 page 74LVC3G14_7 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 — 12 June 2008 9 of 18 NXP Semiconductors 74LVC3G14 Triple inverting Schmitt trigger with 5 V tolerant input 15. Application information The slow input rise and fall times cause additional power dissipation, this can be calculated using the following formula: Padd =fi × (tr ×∆ICC(AV) +tf ×∆ICC(AV)) × VCC where: Padd = additional power dissipation (µW); fi = input frequency (MHz); tr = input rise time (ns); 10 % to 90 %; tf = input fall time (ns); 90 % to 10 %; ∆I CC(AV) = average additional supply current (µA). ∆I CC(AV) differs with positive or negative input transitions, as shown in Figure 13. An example of a relaxation circuit using the 74LVC3G14 is shown in Figure 14. VCC = 3.0 V Fig 12. Typical transfer characteristics 01 0.5 1.5 2 VI (V) 0 14 10 12 8 4 6 2 mdb627 ICC (mA) |
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