Datenblatt-Suchmaschine für elektronische Bauteile |
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CS49311 Datenblatt(PDF) 3 Page - Cirrus Logic |
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CS49311 Datenblatt(HTML) 3 Page - Cirrus Logic |
3 / 90 page CS49300 Family DSP DS339F7 3 8.4 Internal Boot ............................................................................................................. 63 8.5 Application Failure Boot Message ............................................................................ 63 8.6 Resetting the CS493XX ............................................................................................ 63 8.7 External Memory Examples ...................................................................................... 64 8.7.1 Non-Paged Autoboot Memory ...................................................................... 64 8.7.2 32 Kilobyte Paged Autoboot Memory ........................................................... 65 8.8 CDB49300-MEMA.0 ................................................................................................. 66 9. HARDWARE CONFIGURATION ................................................................................... 68 10.DIGITAL INPUT & OUTPUT ........................................................................................... 69 10.1 Digital Audio Formats .............................................................................................. 69 10.1.1 I2S .............................................................................................................. 69 10.1.2 Left Justified ............................................................................................... 69 10.1.3 Multichannel ............................................................................................... 69 10.2 Digital Audio Input Port ........................................................................................... 70 10.3 Compressed Data Input Port ................................................................................... 70 10.4 Byte Wide Digital Audio Data Input ......................................................................... 70 10.4.1 Parallel Delivery with Parallel Control ........................................................ 71 10.4.2 Parallel Delivery with Serial Control ........................................................... 71 10.5 Digital Audio Output Port ......................................................................................... 72 10.5.1 IEC60958 Output ........................................................................................ 73 11.HARDWARE CONFIGURATION ................................................................................... 74 11.1 Address Checking ................................................................................................... 74 11.2 Input Data Hardware Configuration ........................................................................ 74 11.2.1 Input Configuration Considerations ......................................................... 77 11.3 Output Data Hardware Configuration ...................................................................... 78 11.3.1 Output Configuration Considerations ........................................................ 80 11.4 Creating Hardware Configuration Messages .......................................................... 80 12.PIN DESCRIPTIONS ....................................................................................................... 82 13.ORDERING INFORMATION ........................................................................................... 87 14.PACKAGE DIMENSIONS .............................................................................................. 88 15.DOCUMENT REVISIONS ............................................................................................ 89 LIST OF FIGURES Figure 1. RESET Timing ........................................................................................................ 9 Figure 2. CLKIN with CLKSEL = VSS = PLL Enable ............................................................. 9 Figure 3. Intel® Parallel Host Mode Read Cycle .................................................................. 11 Figure 4. Intel® Parallel Host Mode Write Cycle .................................................................. 11 Figure 5. Motorola® Parallel Host Mode Read Cycle ........................................................... 13 Figure 6. Motorola® Parallel Host Mode Write Cycle ........................................................... 13 Figure 7. SPI Control Port Timing ........................................................................................ 15 Figure 8. I2C® Control Port Timing ...................................................................................... 17 Figure 9. Digital Audio Input Data, Master and Slave Clock Timing ..................................... 19 Figure 10. Serial Compressed Data Timing ......................................................................... 20 Figure 11. Parallel Data Timing (when not in a parallel control mode) ................................. 21 Figure 12. Digital Audio Output Data, Input and Output Clock Timing ................................. 23 Figure 13. I2C® Control ........................................................................................................ 29 Figure 14. I2C® Control with External Memory ..................................................................... 30 Figure 15. SPI Control .......................................................................................................... 31 Figure 16. SPI Control with External Memory ...................................................................... 32 Figure 17. Intel® Parallel Control Mode ................................................................................ 33 |
Ähnliche Teilenummer - CS49311 |
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Ähnliche Beschreibung - CS49311 |
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