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CS8427-DZZ Datenblatt(PDF) 10 Page - Cirrus Logic |
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CS8427-DZZ Datenblatt(HTML) 10 Page - Cirrus Logic |
10 / 60 page CS8427 10 DS477F5 SWITCHING CHARACTERISTICS - CONTROL PORT - I²C MODE Note 17, Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF. Notes: 17. I²C protocol is supported only in VL+ = 5.0 V mode. 18. Data must be held for sufficient time to bridge the 25 ns transition time of SCL. Parameter Symbol Min Typ Max Units SCL Clock Frequency fscl - - 100 kHz Bus Free Time Between Transmissions tbuf 4.7 - - μs Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - - μs Clock Low Time tlow 4.7 - - μs Clock High Time thigh 4.0 - - μs Setup Time for Repeated Start Condition tsust 4.7 - - μs SDA Hold Time from SCL Falling (Note 18) thdd 0- - μs SDA Setup Time to SCL Rising tsud 250 - - ns Rise Time of Both SDA and SCL Lines tr - - 25 ns Fall Time of Both SDA and SCL Lines tf - - 25 ns Setup Time for Stop Condition tsusp 4.7 - - μs t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp Stop Start Start Stop Repeated SDA SCL Figure 4. I²C Mode timing |
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