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AD7626 Datenblatt(PDF) 5 Page - Analog Devices

Teilenummer AD7626
Bauteilbeschribung  16-Bit, 10 MSPS, PulSAR Differential ADC
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Hersteller  AD [Analog Devices]
Direct Link  http://www.analog.com
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AD7626
Rev. A | Page 5 of
TIMING SPECIFICATIONS
VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.37 V to 2.63 V; REF = 4.096 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
Time Between Conversions1
tCYC
100
10,000
ns
CNV High Time
tCNVH
10
40
ns
CNV to D (MSB) Ready
tMSB
100
ns
CNV to Last CLK (LSB) Delay
tCLKL
72
ns
CLK Period2
tCLK
3.33
4
(tCYC − tMSB + tCLKL)/n
ns
CLK Frequency
fCLK
250
300
MHz
CLK to DCO Delay (Echoed-Clock Mode)
tDCO
0
4
7
ns
DCO to D Delay (Echoed-Clock Mode)
tD
0
1
ns
CLK to D Delay
tCLKD
0
4
7
ns
1 The maximum time between conversions is 10,000 ns. If CNV± is left idle for a time greater than the maximum value of tCYC, the subsequent conversion result is invalid.
2 For the maximum CLK period, the window available to read data is tCYC − tMSB + tCLKL. Divide this time by the number of bits (n) to be read giving the maximum CLK±
frequency that can be used for a given conversion CNV frequency. In echoed-clock interface mode, n = 16; in self-clocked interface mode, n = 18.


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