Datenblatt-Suchmaschine für elektronische Bauteile |
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CDCE72010 Datenblatt(PDF) 5 Page - Texas Instruments |
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CDCE72010 Datenblatt(HTML) 5 Page - Texas Instruments |
5 / 73 page PACKAGE THERMAL RESISTANCE FOR QFN (RGZ) PACKAGE (1) (2) ABSOLUTE MAXIMUM RATINGS CDCE72010 www.ti.com.............................................................................................................................................................. SCAS858A – JUNE 2008 – REVISED JULY 2009 TERMINAL FUNCTIONS (continued) TERMINAL I/O DESCRIPTION NAME NO. U0P:U0N 7,6 U1P:U1N 10,9 U2P:U2N 13,12 U3P:U3N 21,20 The main outputs of the CDCE72010 are user definable and can be any combination of up U4P:U4N 24,23 O to 9 LVPECL outputs, 9 LVDS outputs, or up to 18 LVCMOS outputs. The outputs are U5P:U5N 27,26 selectable via the SPI interface. The power-up setting is EEPROM configurable. U6P:U6N 30,29 U7P:U7N 36,35 U8P:U8N 39,38 Positive universal output buffer 9 can be 3-stated and used as a positive universal auxiliary U9P or AUXINP 42 I/O input buffer (It requires external termination). The auxiliary input signal can be routed to drive the outputs or the feedback loop to the PLL. Negative universal output buffer 9 can be 3-stated and used as a negative universal U9N or AUXINN 41 I/O auxiliary input buffer (It requires external termination). The auxiliary input signal can be routed to drive the outputs or the feedback loop to the PLL. AIRFLOW θ JP (°C/W) (3) θ JA (°C/W) (LFM) 0 JEDEC compliant board (6×6 VIAs on PAD) 1.5 28 100 JEDEC compliant board (6×6 VIAs on PAD) 1.5 17.6 0 Recommended layout (10×10 VIAs on PAD) 1.5 22.8 100 Recommended layout (10×10 VIAs on PAD) 1.5 13.8 (1) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board). (2) Connected to GND with 9 thermal vias (0.3 mm diameter). (3) θ JP (Junction – Pad) is used for the QFN package, because the main heat flow is from the junction to the GND-pad of the QFN. over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC, AVCC, Supply voltage range(1) –0.5 4.6 V VCC_CP VI Input voltage range(2) –0.5 VCC + 0.5 V VO Output voltage range(2) –0.5 VCC + 0.5 V Input current VI < 0, VI > VCC ±20 mA Output current for LVPECL/LVCMOS Outputs 0 < VO < VCC ±50 mA TJ Junction temperature 125 °C Tstg Storage temperature range –65 150 °C (1) All supply voltages have to be supplied simultaneously. (2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): CDCE72010 |
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