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ADF7021-VBCPZ Datenblatt(PDF) 4 Page - Analog Devices |
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ADF7021-VBCPZ Datenblatt(HTML) 4 Page - Analog Devices |
4 / 60 page ADF7021-V Rev. 0 | Page 4 of 60 SPECIFICATIONS VDD = 2.3 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3 V, TA = 25°C. All measurements are performed with the EVAL-ADF7021-VDBxZ using the PN9 data sequence, unless otherwise noted. The version number of ETSI EN 300 200-1 is V2.3.1. LBW = loop bandwidth and IFBW = IF filter bandwidth. RF AND PLL SPECIFICATIONS Table 1. Parameter Min Typ Max Unit Test Conditions/Comments RF CHARACTERISTICS Phase Frequency Detector (PFD) Frequency RF/256 24 MHz Maximum usable PFD at a particular RF frequency is limited by the minimum N divider value PHASE-LOCKED LOOP (PLL) Normalized In-Band Phase Noise Floor1 −203 dBc/Hz PLL Settling 155 μs Measured for a 100 kHz frequency step to within 5 ppm accuracy, PFD = 19.68 MHz, LBW = 8 kHz EXTERNAL VCO Tuning Range 0.2 2 V Pin L2 Input Sensitivity 0 dBm VCO frequency < 1920 MHz REFERENCE INPUT Crystal Reference2 3.625 24 MHz External Oscillator2, 3 3.625 24 MHz Crystal Start-Up Time4 10 MHz XTAL, 33 pF load capacitors, VDD = 3.0 V XTAL Bias = 20 μA 0.930 ms XTAL Bias = 35 μA 0.438 ms Input Level for External Oscillator OSC1 Pin 0.8 V p-p Clipped sine wave OSC2 Pin CMOS levels V ADC PARAMETERS VDD = 2.3 V to 3.6 V, TA = 25°C Integral Nonlinearity (INL) ±0.4 LSB Differential Nonlinearity (DNL) ±0.4 LSB 1 This value can be used to calculate the in-band phase noise for any operating frequency. Use the following equation to calculate the in-band phase noise performance as seen at the power amplifier (PA) output: −203 + 10 log(fPFD) + 20 logN. 2 Guaranteed by design. Sample tested to ensure compliance. 3 A TCXO, VCXO, or OCXO can be used as an external oscillator. 4 Crystal start-up time is the time from chip enable (CE) being asserted to correct clock frequency on the CLKOUT pin. |
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Ähnliche Beschreibung - ADF7021-VBCPZ |
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