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TDA19989 Datenblatt(PDF) 8 Page - NXP Semiconductors |
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TDA19989 Datenblatt(HTML) 8 Page - NXP Semiconductors |
8 / 47 page TDA19989_1 © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 — 15 February 2010 8 of 47 NXP Semiconductors TDA19989 HDMI 1.3 transmitter with HDCP and CEC support 7.2 Video input formatter 7.2.1 Description TDA19989 has three video input ports VPA[0] to VPA[7], VPB[0] to VPB[7] and VPC[0] to VPC[7]. TDA19989 can accept any of the following video input modes (see Table 6): • RGB, with 8-bit for each component • YCbCr 4 : 4 : 4, with 8-bit for each component • YCbCr 4 : 2 : 2 semi-planar, with up to 12-bit for each component (YCbCr) • YCbCr 4 : 2 : 2 ITU656, with up to 12-bit data depth TDA19989 can be set to latch data at either rising or falling edge, or both. 7.2.2 Internal assignment The aim of the video input processor is to internally map the incoming data to the corresponding mode, which can be handled by the video processing. The internal signal named VP[23:0] is assigned depending on the input mode as defined below. Fig 4. Internal assignment of VP[23:0] Table 3. Internal assignment Internal assignment Internal port RGB YCbCr 4:4:4 YCbCr 4:2:2 semi-planar YCbCr 4:2:2 ITU656 VP[23] G[7] Y[7] Y[11] YCbCr[11] VP[22] G[6] Y[6] Y[10] YCbCr[10] VP[21] G[5] Y[5] Y[9] YCbCr[9] VP[20] G[4] Y[4] Y[8] YCbCr[8] VP[19] G[3] Y[3] Y[7] YCbCr[7] VP[18] G[2] Y[2] Y[6] YCbCr[6] VP[17] G[1] Y[1] Y[5] YCbCr[5] VP[16] G[0] Y[0] Y[4] YCbCr[4] VP[15] B[7] Cb[7] Y[3] YCbCr[3] VP[14] B[6] Cb[6] Y[2] YCbCr[2] VP[13] B[5] Cb[5] Y[1] YCbCr[1] VP[12] B[4] Cb[4] Y[0] YCbCr[0] VIDEO INPUT PROCESSOR 001aah028 VPA[0] to VPA[7] VPB[0] to VPB[7] VP[23:0] VPC[0] to VPC[7] |
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