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TDA19989 Datenblatt(PDF) 10 Page - NXP Semiconductors |
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TDA19989 Datenblatt(HTML) 10 Page - NXP Semiconductors |
10 / 47 page TDA19989_1 © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 — 15 February 2010 10 of 47 NXP Semiconductors TDA19989 HDMI 1.3 transmitter with HDCP and CEC support In the same way: • SWAP_B[2:0] is used to map incoming video port to the internal port VP[19:16]. • SWAP_C[2:0] is used to map incoming video port to the internal port VP[15:12]. • SWAP_D[2:0] is used to map incoming video port to the internal port VP[11:8]. • SWAP_E[2:0] is used to map incoming video port to the internal port VP[7:4]. • SWAP_F[2:0] is used to map incoming video port to the internal port VP[3:0]. The device expects to receive big endian incoming data. However, in cases where the input digital stream to the chip is little endian, the use of the mirror bit of the same register can help to re-order the input bits as described in Table 5. Table 4. Video input swap to VP[23:20] External assignment SWAP_A[2:0] selector value Internal assignment Pin number Pin name Internal port RGB YCbCr 4:4:4 YCbCr 4:2:2 semi-planar YCbCr 4:2:2 ITU656 F3 VPC[7] 000b VP[23] G[7] Y[7] Y0[11] Y1[11] Cb[11] Y0[11] Cr[11] Y1[11] F2 VPC[6] VP[22] G[6] Y[6] Y0[10] Y1[10] Cb[10] Y0[10] Cr[10] Y1[10] F1 VPC[5] VP[21] G[5] Y[5] Y0[9] Y1[9] Cb[9] Y0[9] Cr[9] Y1[9] G1 VPC[4] VP[20] G[4] Y[4] Y0[8] Y1[8] Cb[8] Y0[8] Cr[8] Y1[8] G2 VPC[3] 001b VP[23] G[7] Y[7] Y0[11] Y1[11] Cb[11] Y0[11] Cr[11] Y1[11] G3 VPC[2] VP[22] G[6] Y[6] Y0[10] Y1[10] Cb[10] Y0[10] Cr[10] Y1[10] H2 VPC[1] VP[21] G[5] Y[5] Y0[9] Y1[9] Cb[9] Y0[9] Cr[9] Y1[9] H3 VPC[0] VP[20] G[4] Y[4] Y0[8] Y1[8] Cb[8] Y0[8] Cr[8] Y1[8] C3 VPB[7] 010b VP[23] G[7] Y[7] Y0[11] Y1[11] Cb[11] Y0[11] Cr[11] Y1[11] C2 VPB[6] VP[22] G[6] Y[6] Y0[10] Y1[10] Cb[10] Y0[10] Cr[10] Y1[10] D3 VPB[5] VP[21] G[5] Y[5] Y0[9] Y1[9] Cb[9] Y0[9] Cr[9] Y1[9] D2 VPB[4] VP[20] G[4] Y[4] Y0[8] Y1[8] Cb[8] Y0[8] Cr[8] Y1[8] D1 VPB[3] 011b VP[23] G[7] Y[7] Y0[11] Y1[11] Cb[11] Y0[11] Cr[11] Y1[11] E1 VPB[2] VP[22] G[6] Y[6] Y0[10] Y1[10] Cb[10] Y0[10] Cr[10] Y1[10] E2 VPB[1] VP[21] G[5] Y[5] Y0[9] Y1[9] Cb[9] Y0[9] Cr[9] Y1[9] E3 VPB[0] VP[20] G[4] Y[4] Y0[8] Y1[8] Cb[8] Y0[8] Cr[8] Y1[8] A4 VPA[7] 100b VP[23] G[7] Y[7] Y0[11] Y1[11] Cb[11] Y0[11] Cr[11] Y1[11] B4 VPA[6] VP[22] G[6] Y[6] Y0[10] Y1[10] Cb[10] Y0[10] Cr[10] Y1[10] A3 VPA[5] VP[21] G[5] Y[5] Y0[9] Y1[9] Cb[9] Y0[9] Cr[9] Y1[9] B3 VPA[4] VP[20] G[4] Y[4] Y0[8] Y1[8] Cb[8] Y0[8] Cr[8] Y1[8] A2 VPA[3] 101b VP[23] G[7] Y[7] Y0[11] Y1[11] Cb[11] Y0[11] Cr[11] Y1[11] B2 VPA[2] VP[22] G[6] Y[6] Y0[10] Y1[10] Cb[10] Y0[10] Cr[10] Y1[10] B1 VPA[1] VP[21] G[5] Y[5] Y0[9] Y1[9] Cb[9] Y0[9] Cr[9] Y1[9] C1 VPA[0] VP[20] G[4] Y[4] Y0[8] Y1[8] Cb[8] Y0[8] Cr[8] Y1[8] |
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