Technical Note

7/17

www.rohm.com

2010.06 - Rev.A

© 2010 ROHM Co., Ltd. All rights reserved.

BD3811K1,BD3818KS

CL

(CLOCK）

DA

DATA

LATCH

thd

thd

th

ts

tsl

thl

tsd

twc

twh

twd

twl

DATA

DATA

LATCH

90%

90%

90%

90%

10%

10%

10%

90%

90%

90%

90%

90%

10%

10%

10%

twc

Terminate

with LOW

●

Timing chart

1. Signal Timing Conditions

・

Data is read on the rising edge of the clock.

・

Latch is read on the falling edge of the clock.

・

Latch signal must terminate with the LOW state.

* To avoid malfunctions, clock and data signals must terminate with the LOW state.

Fig.1

Parameter

Symbol

Limits

Unit

Min.

Typ.

Max.

Minimum Clock Width

twc

2.0

-

-

µS

Minimum Data Width

twd

2.0

-

-

µS

Minimum Latch Width

twl

2.0

-

-

µS

LOW Hold Width

twh

2.0

-

-

µS

Data Set-up Time (DATA

CLK)

tsd

1.0

-

-

µS

Data Hold Time (CLK

DATA)

thd

1.0

-

-

µS

Latch Set-up Time (CLK

LATCH)

tsl

1.0

-

-

µS

Latch Hold Time (DATA

LATCH)

thl

1.0

-

-

µS

Latch Low Set-up Time

ts

1.0

-

-

µS

Latch Low Hold Time

th

1.0

-

-

µS

2. External Mute (Pin48) Voltage (BD3811K1)

Parameter

Limits

Unit

Conditions

Min.

Typ.

Max.(

Vcc)

Volume Mute OFF

0

－

1.0

V

Vcc=5 to 7.3V

VEE=-5 to -7.3V

Volume Mute ON

2.2

－

5.5

3. Voltage Conditions for Control Signals

Parameter

Limits

Unit

Conditions

BD3811K1

BD3818KS

Min.

Typ.

Max.

(

Vcc)

Min.

Typ.

Max.

(

Vcc)

“H” Input Voltage

2.2

－

5.5

3.0

－

5.5

V

Vcc=5 to 7.4V

VEE=-5 to -7.4V

“L” Input Voltage

0

－

1.0

0

－

1.5

V