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ADM1034ARQZ-REEL Datenblatt(PDF) 10 Page - ON Semiconductor |
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ADM1034ARQZ-REEL Datenblatt(HTML) 10 Page - ON Semiconductor |
10 / 39 page ADM1034 http://onsemi.com 10 Table 3. UDID Values Bit No. Name Function Value <127:120> Device Capabilities Describes the ADM1034’s capabilities (for instance, that it supports PEC and uses a random number address device). 11000001 <119:112> Version/Revision UDID version number (Version 1) and silicon revision identification 00001010 <111:96> Vendor ID Analog Devices vendor ID number, as assigned by the SBS Implementer’s Forum or the PCI SIG. 00010001 11010100 <95:80> Device ID Device ID. 00010000 00110100 <79:64> Interface Identifies the protocol layer interfaces supported by the ADM1034. This represents SMBus 2.0 as the Interface version.. 00000000 00000100 <63:48> Subsystem Vendor ID Subsystem Vendor ID = 0 (subsystem fields are unsupported). 00000000 00000000 <47:32> Subsystem Device ID Subsystem Device ID = 0 (subsystem fields are unsupported). 00000000 00000000 <31:0> Vendor Specific ID A unique number per device. Contains LOCATION information (LL) and a 16−bit random number (x). See Table 5 for information on setting the LLL bits. 00000000 00000LLL xxxxxxxx xxxxxxxx SMBus 2.0 Fixed and Discoverable Mode The ADM1034 also supports fixed and discoverable mode, which is backwards compatible with SMBus 1.0 and 1.1. Fixed and discoverable mode supports all the same functionality as ARP−capable mode, except for assign address in which case it powers up with a fixed address and is not changed by the assign address call. The fixed address is determined by the state of the LOCATION pin on powerup. SMBus 2.0 Read and Write Operations The master initiates data transfer by establishing a start condition, defined as a high−to−low transition on the serial data line (SDA) while the serial clock line (SCL) remains high. This indicates that an address/data stream is to follow. All slave peripherals connected to the serial bus respond to the start condition and shift in the next 8 bits, which consist of a 7−bit address (MSB first) plus an R/W bit. This last bit determines the direction of the data transfer (whether data is written to or read from the slave device). 1. The peripheral that corresponds to the transmitted address responds by pulling the data line low during the low period before the 9th clock pulse, which is known as the acknowledge bit. All other devices on the bus remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is a 0, the master writes to the slave device. If the R/W bit is a 1, the master reads from it. 2. Data is sent over the serial bus in sequences of 9 clock pulses − 8 bits of data followed by an acknowledge bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low−to−high transition when the clock is high may be interpreted as a stop signal. The number of data bytes that can be transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. 3. When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device overrides the acknowledge bit by pulling the data line high during the low period before the 9th clock pulse. This is known as no acknowledge. The master takes the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a stop condition. It is not possible to mix read and write in one operation, because the type of operation is determined at the beginning and cannot be changed without starting a new operation. To write data to one of the device data registers or to read data from it, the address pointer register (APR) must be set so that the correct data register is addressed; then data can be written into that register or read from it. The first byte of a write operation always contains an address that is stored in the APR. If data is to be written to the device, then the write operation contains a second data byte, which is written to the register selected by the APR. As illustrated in Figure 17, the device address is sent over the bus, followed by R/W set to 0. This is followed by two data bytes. The first data byte is the address of the internal data register to be written to, which is stored in the APR. The second data byte is the data to be written to the internal data register. When reading data from a register there are two possibilities. If the ADM1034’s APR value is unknown or incorrect, it must be set to the correct value before data can be read from the desired data register. To do this, perform a write to the |
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