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CAT24C03 Datenblatt(PDF) 8 Page - ON Semiconductor

Teilenummer CAT24C03
Bauteilbeschribung  2-Kb and 4-Kb I2C Serial EEPROM with Partial Array Write Protection
Download  14 Pages
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Hersteller  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

CAT24C03 Datenblatt(HTML) 8 Page - ON Semiconductor

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CAT24C03, CAT24C05
http://onsemi.com
8
READ OPERATIONS
Immediate Read
Upon receiving a Slave address with the R/W bit set to ‘1’,
the CAT24C03/05 will interpret this as a request for data
residing at the current byte address in memory. The
CAT24C03/05 will acknowledge the Slave address, will
immediately shift out the data residing at the current address,
and will then wait for the Master to respond. If the Master
does not acknowledge the data (NoACK) and then follows
up with a STOP condition (Figure 10), the CAT24C03/05
returns to Standby mode.
Selective Read
Selective Read operations allow the Master device to
select at random any memory location for a read operation.
The Master device first performs a ‘dummy’ write operation
by sending the START condition, slave address and byte
address of the location it wishes to read. After the
CAT24C03/05 acknowledges the byte address, the Master
device resends the START condition and the slave address,
this time with the R/W bit set to one. The CAT24C03/05 then
responds with its acknowledge and sends the requested data
byte. The Master device does not acknowledge the data
(NoACK) but will generate a STOP condition (Figure 11).
Sequential Read
If during a Read session, the Master acknowledges the 1st
data byte, then the CAT24C03/05 will continue transmitting
data residing at subsequent locations until the Master
responds with a NoACK, followed by a STOP (Figure 12).
In contrast to Page Write, during Sequential Read the
address count will automatically increment to and then
wrap−around at end of memory (rather than end of page).
SCL
SDA
8th Bit
STOP
NO ACK
DATA OUT
89
SLAVE
ADDRESS
S
A
C
K
D ATA
BYTE
N
O
A
C
K
S
T
O
P
P
S
T
A
R
T
BUS ACTIVITY:
MASTER
SLAVE
Figure 10. Immediate Read Sequence and Timing
SLAVE
S
A
C
K
N
O
A
C
K
S
T
O
P
P
S
T
A
R
T
S
A
C
K
SLAVE
ADDRESS
A
C
K
S
T
A
R
T
D ATA
BYTE
ADDRESS
BYTE
ADDRESS
BUS ACTIVITY:
MASTER
SLAVE
Figure 11. Selective Read Sequence
S
T
O
P
P
SLAVE
ADDRESS
A
C
K
A
C
K
A
C
K
N
O
A
C
K
A
C
K
D ATA
BYTE
n
D ATA
BYTE
n+1
D ATA
BYTE
n+2
D ATA
BYTE
n+x
BUS ACTIVITY:
MASTER
SLAVE
Figure 12. Sequential Read Sequence


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