Datenblatt-Suchmaschine für elektronische Bauteile
  German  ▼
ALLDATASHEETDE.COM

X  

CAT24C03VP2I-GT3 Datenblatt(PDF) 4 Page - ON Semiconductor

Teilenummer CAT24C03VP2I-GT3
Bauteilbeschribung  2-Kb and 4-Kb I2C Serial EEPROM with Partial Array Write Protection
Download  14 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Hersteller  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

CAT24C03VP2I-GT3 Datenblatt(HTML) 4 Page - ON Semiconductor

  CAT24C03VP2I-GT3 Datasheet HTML 1Page - ON Semiconductor CAT24C03VP2I-GT3 Datasheet HTML 2Page - ON Semiconductor CAT24C03VP2I-GT3 Datasheet HTML 3Page - ON Semiconductor CAT24C03VP2I-GT3 Datasheet HTML 4Page - ON Semiconductor CAT24C03VP2I-GT3 Datasheet HTML 5Page - ON Semiconductor CAT24C03VP2I-GT3 Datasheet HTML 6Page - ON Semiconductor CAT24C03VP2I-GT3 Datasheet HTML 7Page - ON Semiconductor CAT24C03VP2I-GT3 Datasheet HTML 8Page - ON Semiconductor CAT24C03VP2I-GT3 Datasheet HTML 9Page - ON Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 4 / 14 page
background image
CAT24C03, CAT24C05
http://onsemi.com
4
Power−On Reset (POR)
The CAT24C03/05 incorporates Power−On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state.
The CAT24C03/05 device will power up into Standby
mode after VCC exceeds the POR trigger level and will
power down into Reset mode when VCC drops below the
POR trigger level. This bi−directional POR feature protects
the device against ‘brown−out’ failure following a
temporary loss of power.
Pin Description
SCL: The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA: The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this pin
is open drain. Data is acquired on the positive edge, and is
delivered on the negative edge of SCL.
A0, A1 and A2: The Address inputs set the device address
when cascading multiple devices. When not driven, these
pins are pulled LOW internally.
WP: The Write Protect input pin inhibits the write
operations for upper half of memory, when pulled HIGH.
When not driven, this pin is pulled LOW internally.
Functional Description
The CAT24C03/05 supports the Inter−Integrated Circuit
(I2C) Bus data transmission protocol, which defines a device
that sends data to the bus as a transmitter and a device
receiving data as a receiver. Data flow is controlled by a
Master device, which generates the serial clock and all
START and STOP conditions. The CAT24C03/05 acts as a
Slave device. Master and Slave alternate as either
transmitter or receiver.
I2C Bus Protocol
The I2C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the VCC supply via pull−up
resistors. Master and Slave devices connect to the 2−wire
bus via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is high. An SDA transition while SCL is
HIGH will be interpreted as a START or STOP condition
(Figure 2). The START condition precedes all commands. It
consists of a HIGH to LOW transition on SDA while SCL
is HIGH. The START acts as a ‘wake−up’ call to all
receivers. Absent a START, a Slave will not respond to
commands. The STOP condition completes all commands.
It consists of a LOW to HIGH transition on SDA while SCL
is HIGH.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8−bit
serial Slave address. For normal Read/Write operations, the
first 4 bits of the Slave address are fixed at 1010 (Ah). The
next 3 bits are used as programmable address bits when
cascading multiple devices and/or as internal address bits.
The last bit of the slave address, R/W, specifies whether a
Read (1) or Write (0) operation is to be performed. The 3
address space extension bits are assigned as illustrated in
Figure 3. A2, A1 and A0 must match the state of the external
address pins, and a8 (CAT24C05) is internal address bit.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA line
during the 9th clock cycle (Figure 4). The Slave will also
acknowledge the address byte and every data byte presented
in Write mode. In Read mode the Slave shifts out a data byte,
and then releases the SDA line during the 9th clock cycle. As
long as the Master acknowledges the data, the Slave will
continue transmitting. The Master terminates the session by
not acknowledging the last data byte (NoACK) and by
issuing a STOP condition. Bus timing is illustrated in
Figure 5.


Ähnliche Teilenummer - CAT24C03VP2I-GT3

HerstellerTeilenummerDatenblattBauteilbeschribung
logo
Catalyst Semiconductor
CAT24C03VP2I-GT3 CATALYST-CAT24C03VP2I-GT3 Datasheet
401Kb / 20P
   2-Kb I2C CMOS Serial EEPROM with Partial Array Write Protection
CAT24C03VP2I-GT3 CATALYST-CAT24C03VP2I-GT3 Datasheet
434Kb / 18P
   2-Kb and 4-Kb I2C Serial EEPROM with Partial Array Write Protection
CAT24C03VP2I-GT3 CATALYST-CAT24C03VP2I-GT3 Datasheet
370Kb / 17P
   1-Kb, 2-Kb, 4-Kb, 8-Kb and 16-Kb CMOS Serial EEPROM
More results

Ähnliche Beschreibung - CAT24C03VP2I-GT3

HerstellerTeilenummerDatenblattBauteilbeschribung
logo
Catalyst Semiconductor
CAT24C03 CATALYST-CAT24C03_06 Datasheet
434Kb / 18P
   2-Kb and 4-Kb I2C Serial EEPROM with Partial Array Write Protection
CAT24C05 CATALYST-CAT24C05 Datasheet
434Kb / 18P
   2-Kb and 4-Kb I2C Serial EEPROM with Partial Array Write Protection
CAT24C03 CATALYST-CAT24C03 Datasheet
401Kb / 20P
   2-Kb I2C CMOS Serial EEPROM with Partial Array Write Protection
logo
ON Semiconductor
CAT24WC66 ONSEMI-CAT24WC66 Datasheet
147Kb / 11P
   64-Kb I2C Serial EEPROM with Partial Array Write Protection
August, 2009 ??Rev. 10
logo
Catalyst Semiconductor
CAT24WC66 CATALYST-CAT24WC66_06 Datasheet
155Kb / 13P
   64K-bit I2C Serial EEPROM with Partial Array Write Protection
logo
ON Semiconductor
CAV24C02 ONSEMI-CAV24C02_15 Datasheet
122Kb / 15P
   2-Kb, 4-Kb, 8-Kb and 16-Kb I2C CMOS Serial EEPROM
November, 2015 ??Rev. 4
N24C02 ONSEMI-N24C02 Datasheet
95Kb / 10P
   2-Kb, 4-Kb, 8-Kb and 16-Kb I2C CMOS Serial EEPROM
June, 2016 ??Rev. 1
CAV24C02YE-GT3 ONSEMI-CAV24C02YE-GT3 Datasheet
148Kb / 11P
   2-Kb, 4-Kb, 8-Kb and 16-Kb I2C CMOS Serial EEPROM
May, 2011 ??Rev. 2
CAV24C02 ONSEMI-CAV24C02 Datasheet
151Kb / 11P
   2-Kb, 4-Kb, 8-Kb and 16-Kb I2C CMOS Serial EEPROM
April, 2011 ??Rev. 1
CAT24C01 ONSEMI-CAT24C01_16 Datasheet
182Kb / 23P
   1-Kb, 2-Kb, 4-Kb, 8-Kb and 16-Kb I2C CMOS Serial EEPROM
November, 2016 ??Rev. 31
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14


Datenblatt Download

Go To PDF Page


Link URL




Privatsphäre und Datenschutz
ALLDATASHEETDE.COM
War ALLDATASHEET hilfreich?  [ DONATE ] 

Über Alldatasheet   |   Werbung   |   Kontakt   |   Privatsphäre und Datenschutz   |   Linktausch   |   Hersteller
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com