Datenblatt-Suchmaschine für elektronische Bauteile |
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CAT150029MWI-GT3 Datenblatt(PDF) 11 Page - ON Semiconductor |
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CAT150029MWI-GT3 Datenblatt(HTML) 11 Page - ON Semiconductor |
11 / 15 page CAT15002, CAT15004 © 2008 SCILLC. All rights reserved. 11 Doc. No. MD-1126 Rev. B Characteristics subject to change without notice READ OPERATIONS Read from Memory Array To read from memory, the host sends a READ instruction followed by an 8-bit address (for the CAT15008, bit 3 of the Read instruction opcode contains address bit A8). After receiving the last address bit, the CAT15002/04 will respond by shifting out data on the SO pin (as shown in Figure 10). Sequentially stored data can be read out by simply continuing to run the clock. The internal address pointer is automatically incremented to the next higher address as data is shifted out. After reaching the highest memory address, the address counter “rolls over” to the lowest memory address, and the read cycle can be continued indefinitely. The read operation is terminated by taking CS ¯¯ high. Read Status Register To read the status register, the host simply sends a RDSR command. After receiving the last bit of the command, the CAT15002/04 will shift out the contents of the status register on the SO pin (Figure 11). The status register may be read at any time, including during an internal write cycle. Figure 10. READ Timing Notes: * Please check the instruction set table for address X = 0 for CAT15002; X=A8 for CAT15004 Dashed Line = mode (1, 1) - - - - - - Figure 11. RDSR Timing Note: Dashed Line = mode (1, 1) - - - - - - 01 2 3 4 5 6 78 10 911 12 13 14 SCK SI DATA OUT MSB HIGH IMPEDANCE OPCODE SO 7 6 5 4 3 2 1 0 CS 00 0 00 1 0 1 21 22 SCK SI SO 00 00 001 1 BYTE ADDRESS 0 1 2 3 4 5 6 7 8 9 10 121314 1516 1718 1920 D7 D6 D5 D4 D3 D2 D1 D0 CS OPCODE DATA OUT MSB HIGH IMPEDANCE 11 A7 A6 A5 A4 A3 A2 A1 A0 X* |
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