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CAT150089JWI-GT3 Datenblatt(PDF) 6 Page - ON Semiconductor

Teilenummer CAT150089JWI-GT3
Bauteilbeschribung  Voltage Supervisor with 8-Kb and 16-Kb SPI Serial CMOS EEPROM
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Hersteller  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

CAT150089JWI-GT3 Datenblatt(HTML) 6 Page - ON Semiconductor

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CAT15008, CAT15016
Doc. No. MD-1125 Rev. B
6
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
Figure 2 shows the maximum pulse duration of
negative-going VCC transients that do not cause a reset
condition. As the amplitude of the transient goes further
below the threshold (increasing VTH - VCC), the
maximum pulse duration decreases. In this test, the
VCC starts from an initial voltage of 0.5V above the
threshold and drops below it by the amplitude of the
overdrive voltage (VTH - VCC).
EMBEDDED EEPROM DESCRIPTION
The CAT15008/16 devices support the Serial Peripheral
Interface (SPI) bus protocol, modes (0,0) and (1,1). The
device contains an 8-bit instruction register. The
instruction set and associated op-codes are listed in
Table 1.
Reading data stored in the CAT15008/16 is accom–
plished by simply providing the READ command and an
address. Writing to the CAT15008/16, in addition to a
WRITE command, address and data, also requires
enabling the device for writing by first setting certain bits
in a Status Register, as will be explained later.
After a high to low transition on the CS
¯¯ input pin, the
CAT15008/16 will accept any one of the six instruction
op-codes listed in Table 1 and will ignore all other
possible
8-bit
combinations.
The
communication
protocol follows the timing from Figure 3.
Figure 2. Maximum Transient Duration without
Causing a Reset Pulse vs. Overdrive Voltage
Table 1: Instruction Set
Instruction
Opcode
Operation
WREN
0000 0110
Enable Write Operations
WRDI
0000 0100
Disable Write Operations
RDSR
0000 0101
Read Status Register
WRSR
0000 0001
Write Status Register
READ
0000 0011
Read Data from Memory
WRITE
0000 0010
Write Data to Memory
Figure 3. Synchronous Data Timing
Note: Dashed Line = mode (1, 1) - - - - - -
VALID IN
VIH
VIL
tCSS
VIH
VIL
VIH
VIL
VOH
VOL
HI-Z
tSU
tH
tWH
tWL
tV
tCS
tCSH
tHO
tDIS
HI-Z
CS
SCK
SI
SO
tRI
tFI
RESET OVERDRIVE VTH - VCC [mV]
TAMB = 25ºC
CAT150xxM
CAT150xxZ


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