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MC74HC73ADTR2G Datenblatt(PDF) 1 Page - ON Semiconductor |
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MC74HC73ADTR2G Datenblatt(HTML) 1 Page - ON Semiconductor |
1 / 9 page © Semiconductor Components Industries, LLC, 2009 December, 2009 − Rev. 7 1 Publication Order Number: MC74HC73/D MC74HC73A Dual J-K Flip-Flop with Reset High−Performance Silicon−Gate CMOS The MC74HC73A is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip−flop is negative−edge clocked and has an active−low asynchronous reset. The MC74HC73A is identical in function to the HC107, but has a different pinout. Features • Output Drive Capability: 10 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 mA • High Noise Immunity Characteristic of CMOS Devices • In Compliance with the JEDEC Standard No. 7.0 A Requirements • Chip Complexity: 92 FETs or 23 Equivalent Gates • These are Pb−Free Devices PIN ASSIGNMENT FUNCTION TABLE LOGIC DIAGRAM PIN 4 = VCC PIN 11 = GND RESET 2 K2 CLOCK 2 J2 RESET 1 K1 CLOCK 1 J1 Q2 Q2 Q1 Q1 14 1 3 2 7 5 10 6 12 13 9 8 11 12 13 14 8 9 10 5 4 3 2 1 7 6 K2 GND Q1 Q1 J1 Q2 Q2 VCC K1 RESET 1 CLOCK 1 J2 RESET 2 CLOCK 2 Inputs Outputs Reset Clock J K Q Q L XXX L H H L L No Change HL H L H HH L H L H H H Toggle H L X X No Change H H X X No Change H X X No Change http://onsemi.com MARKING DIAGRAMS A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package TSSOP−14 DT SUFFIX CASE 948G 14 1 SOIC−14 D SUFFIX CASE 751A 14 1 HC73AG AWLYWW 1 14 HC 73A ALYWG G 1 14 14 1 PDIP−14 N SUFFIX CASE 646 MC74HC73AN AWLYYWWG 1 14 See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ORDERING INFORMATION (Note: Microdot may be in either location) |
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