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SN74AUC1G74DCTR Datenblatt(PDF) 1 Page - Texas Instruments

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Teilenummer SN74AUC1G74DCTR
Bauteilbeschribung  SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
Download  16 Pages
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Hersteller  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

SN74AUC1G74DCTR Datenblatt(HTML) 1 Page - Texas Instruments

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FEATURES
Seemechanicaldrawingsfordimensions.
CLR
3
2
5
8
1
CLK
VCC
D
GND
DCUPACKAGE
(TOP VIEW)
Q
PRE
Q
4
6
7
DCTPACKAGE
(TOP VIEW)
3
2
4
5
1
CLK
VCC
PRE
D
GND
Q
CLR
Q
6
7
8
YZPOR YZTPACKAGE
(BOTTOM VIEW)
D
GND
VCC
Q
Q
2
5
3
4
8
6
1
7
CLK
CLR
PRE
RSEPACKAGE
(TOP VIEW)
VCC
GND
4
8
DESCRIPTION/ORDERING INFORMATION
SN74AUC1G74
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCES537D – DECEMBER 2003 – REVISED JUNE 2007
• Available in the Texas Instruments
• Low Power Consumption, 10-μA Max I
CC
NanoFree™ Package
• ±8-mA Output Drive at 1.8 V
• Optimized for 1.8-V Operation and Is 3.6-V I/O
• Latch-Up Performance Exceeds 100 mA Per
Tolerant to Support Mixed-Mode Signal
JESD 78, Class II
Operation
• ESD Protection Exceeds JESD 22
• I
off Supports Partial-Power-Down Mode
2000-V Human-Body Model (A114-A)
Operation
200-V Machine Model (A115-A)
• Sub-1-V Operable
1000-V Charged-Device Model (C101)
• Max t
pd of 1.5 ns at 1.8 V
This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed
specifically for 1.65-V to 1.95-V VCC operation.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for
higher frequencies, the CLR input overrides the PRE input when they are both low.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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