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74AUP1G125DBVRE4 Datenblatt(PDF) 10 Page - Texas Instruments

Teilenummer 74AUP1G125DBVRE4
Bauteilbeschribung  LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
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Hersteller  TI [Texas Instruments]
Direct Link  http://www.ti.com
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74AUP1G125DBVRE4 Datenblatt(HTML) 10 Page - Texas Instruments

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NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. All parameters and waveforms are not applicable to all devices.
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
VCC = 1.2 V
± 0.1 V
VCC = 0.8 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
CL
VM
VI
V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.3 V
Output
Waveform 1
S1 at 2
× VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VCC
0 V
VOL + V
VOH − V
≈0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Control
VCC/2
VCC/2
VCC/2
VCC/2
tPLZ/tPZL
tPHZ/tPZH
2
× VCC
GND
TEST
S1
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
GND
5 k
5 k
2
× VCC
SN74AUP1G125
SCES595J – JULY 2004 – REVISED MARCH 2010
www.ti.com
PARAMETER MEASUREMENT INFORMATION
(Enable and Disable Times)
Figure 4. Load Circuit and Voltage Waveforms
10
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Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP1G125


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