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CDCEL925PWRG4 Datenblatt(PDF) 2 Page - Texas Instruments

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Teilenummer CDCEL925PWRG4
Bauteilbeschribung  PROGRAMMABLE 2-PLL VCXO CLOCK SYNTHESIZER WITH 1.8-V, 2.5-V and 3.3-V LVCMOS OUTPUTS
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Hersteller  TI [Texas Instruments]
Direct Link  http://www.ti.com
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CDCE925
CDCEL925
SCAS847F – JULY 2007 – REVISED MARCH 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION
The CDCE925 and CDCEL925 are modular PLL-based low-cost, high-performance, programmable clock
synthesizers, multipliers, and dividers. They generate up to five output clocks from a single input frequency. Each
output can be programmed in-system for any clock frequency up to 230 MHz, using up to two independent
configurable PLLs.
The CDCx925 has separate output supply pins, VDDOUT, which is 1.8 V for CDCEL925 and 2.5 V to 3.3 V for
CDCE925.
The input accepts an external crystal or LVCMOS clock signal. In case of a crystal input, an on-chip load
capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 pF to 20 pF.
Additionally, an on-chip VCXO is selectable which allows synchronization of the output frequency to an external
control signal, that is, PWM signal.
The deep M/N divider ratio allows the generation of zero-ppm audio/video, networking (WLAN, BlueTooth,
Ethernet, GPS) or interface (USB, IEEE1394, Memory Stick) clocks from a 27 MHz reference input frequency, for
example.
All PLLs supports SSC (spread-spectrum clocking). SSC can be center-spread or down-spread clocking which is
a common technique to reduce electro-magnetic interference (EMI).
Based on the PLL frequency and the divider settings, the internal loop filter components are automatically
adjusted to achieve high stability and optimized jitter transfer characteristic of each PLL.
The device supports nonvolatile EEPROM programming for easy customization of the device in the application. It
is preset to a factory default configuration and can be re-programmed to a different application configuration
before it goes onto the PCB or re-programmed by in-system programming. All device settings are programmable
through SDA/SCL bus, a 2-wire serial interface.
Three, free programmable control inputs, S0, S1, and S2, can be used to select different frequencies, or change
SSC setting for lowering EMI, or other control features like outputs disable to low, outputs 3-state, power down,
PLL bypass, etc.).
The CDCx925 operates in a 1.8 V environment. It operates in a temperature range of –40 °C to 85 °C.
Terminal Functions for CDCE925, CDCEL925
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Y1, Y2, ... Y5
7, 8, 10, 11, 13
O
LVCMOS outputs
Xin/CLK
1
I
Crystal oscillator input or LVCMOS clock Input (selectable via SDA/SCL bus)
Xout
16
O
Crystal oscillator output (leave open or pullup when not used)
VCtrl
4
I
VCXO control voltage (leave open or pullup when not used)
VDD
3
Power
1.8-V power supply for the device
CDCEL925: 1.8-V supply for all outputs
VDDOUT
6, 9
Power
CDCE925: 3.3-V or 2.5-V supply for all outputs
GND
5, 12
Ground
Ground
S0
2
I
User-programmable control input S0; LVCMOS inputs; internal pullup
SDA: bidirectional serial data input/output (default configuration), LVCMOS; internal
SDA/S1
15
I/O or I
pullup; or
S1: user-programmable control input; LVCMOS inputs; internal pullup
SCL: serial clock input (default configuration), LVCMOS; internal pullup or
SCL/S2
14
I
S2: user-programmable control input; LVCMOS inputs; internal pullup
2
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Copyright © 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): CDCE925 CDCEL925


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