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SN74AUP1G74DCURG4 Datenblatt(PDF) 2 Page - Texas Instruments

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Teilenummer SN74AUP1G74DCURG4
Bauteilbeschribung  LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
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Hersteller  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

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AUP
LVC
AUP
AUP
LVC
Static-Power Consumption
(
µA)
Dynamic-Power Consumption
(pF)
Single, dual, and triple gates
3.3-V
Logic
3.3-V
Logic
0%
20%
40%
60%
80%
100%
0%
20%
40%
60%
80%
100%
−0.5
0
0.5
1
1.5
2
2.5
3
3.5
0
5
10
15
20
25
30
35
40
45
Time − ns
AUP1G08 data at CL = 15 pF
Output
Input
Switching Characteristics
at 25 MHz
SN74AUP1G74
SCES644C – MARCH 2006 – REVISED MARCH 2010
www.ti.com
Figure 1. AUP – The Lowest-Power Family
Figure 2. Excellent Signal Integrity
This single positive-edge-triggered D-type flip-flop is designed for 0.8-V to 3.6-V VCC operation.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for
higher frequencies, the CLR input overrides the PRE input when they are both low.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING(3)
NanoStar™ – WCSP (DSBGA)
Reel of 3000
SN74AUP1G74YFPR
_ _ _HS_
0.23-mm Large Bump – YFP
NanoStar™ – WCSP (DSBGA)
Reel of 3000
SN74AUP1G74YZPR
_ _ _HS_
0.23-mm Large Bump – YZP (Pb-free)
–40°C to 85°C
SSOP – DCT
Reel of 3000
SN74AUP1G74DCTR
H74_ _ _
VSSOP – DCU
Reel of 3000
SN74AUP1G74DCUR
H74_
uQFN – DQE
Reel of 5000
SN74AUP1G74DQER
HS
QFN – RSE
Reel of 5000
SN74AUP1G74RSER
HS
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2)
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3)
DCT: The actual top-side marking has three additional characters that designate the year, month, and wafer fab/assembly site.
DCU: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
X
L
X
X
L
H
H
H
H
H
L
H
H
L
L
H
H
H
L
X
Q0
Q 0
2
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Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP1G74


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