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CS1500 Datenblatt(PDF) 9 Page - Cirrus Logic |
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CS1500 Datenblatt(HTML) 9 Page - Cirrus Logic |
9 / 22 page CS1500 DS849A7 9 Jul ?$shortyear> CONFIDENTIAL Figure 14. Burst Modes 3.4 Output Power and PFC Boost Inductor Maximum output power in normal mode is defined by the following equation: where, Vin(min), Vlink, and LB are user defined based on application requirements and maximum operating switching frequency fmax = 70kHz. α is a margin factor to guarantee rated power (Po) against tolerances and transients. α is typically set to 0.9. The PFC Boost Inductor (LB in Figure 21) value can be calculated using Equation 1 as follows: where Vin(min) is volts RMS, Vlink is volts DC, and α is set to 0.9. 3.5 PFC Output Capacitor The value of the PFC output capacitor should be chosen based upon voltage ripple and hold-up requirements. This is described in more detail in the application section 4.1.6 PFC Output Capacitor on page 13. To ensure system stability with the digital controller, the recommended value of the capacitor is within the range of 0.5 μF / watt to 2.0 μF/watt. 3.6 Output Feedback & Regulation A current proportional to the PFC output voltage, Vlink, is supplied to the IC on pin FB and is used as a feedback control signal. This current is compared against a fixed-value internal reference current, Iref. Resistor RFB (shown as R2a & R2b in Figure 21) sets the feedback current and is calculated as follows: Figure 15. Feedback Input Pin Model The ADC is used to measure the magnitude of the IFB current through resistor RFB. The magnitude of the IFB current is then compared to an internal reference current, Iref. By using digital loop compensation, the voltage feedback signal does not require an external compensation network. It is recommended that a ceramic capacitor of up to 2.2 nF be placed between the FB pin and the VDD pin to filter noise in the layout. 3.7 IAC Signal Figure 16. IAC Input Pin Model A current proportional to the AC input voltage is supplied to the IC on pin IAC and is used by the PFC control algorithm. Resistor RAC (shown as R1a & R1b in Figure 21) sets the IAC current and is calculated as follows: For optimal performance, resistor RAC, RFB should use less than 1% tolerance resistor. Resistors can be separated in two Vin [V] t [ms] FET Vgs Burst Mode Active Vin Po [W] t [ms] PFC Disable Burst Threshold Po αη V in min () () × 2 × V link V in min () 2 × () – 2f max L B V link × × × --------------------------------------------------------- × = [Eq.1] L B αη V in min () () × 2 × V link V in min () 2 × () – 2f max Po V link × × × --------------------------------------------------------- × = [Eq.2] R FB V link V dd – I ref ---------------------------- = [Eq.3] RFB IFB VDD ADC Vlink 7 FB 4 RAC IAC IAC VDD ADC 7 3 Vrect R AC R FB = [Eq.4] |
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