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TL16C2550IRHBRG4 Datenblatt(PDF) 6 Page - Texas Instruments

Teilenummer TL16C2550IRHBRG4
Bauteilbeschribung  1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS
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Hersteller  TI [Texas Instruments]
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TL16C2550IRHBRG4 Datenblatt(HTML) 6 Page - Texas Instruments

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RCV
FIFO
Serial to
Parallel
Flow
Control
XMT
FIFO
Parallel
to Serial
Flow
Control
Parallel
to Serial
Flow
Control
Serial to
Parallel
Flow
Control
XMT
FIFO
RCV
FIFO
ACE1
ACE2
D7 −D0
RX
TX
RTS
CTS
TX
RX
CTS
RTS
D7 −D0
Auto-CTS (See Figure 2)
Auto-RTS (See Figure 3 and Figure 4)
Enabling Autoflow Control and Auto-CTS
Auto-CTS and Auto-RTS Functional Timing
Start
Bits 0 −7
Start
Bits 0 −7
Start
Bits 0 −7
Stop
Stop
Stop
SOUT
CTS
TL16C2550
SLWS161D – JUNE 2005 – REVISED OCTOBER 2006
Figure 1. Autoflow Control (Auto-RTS and Auto-CTS) Example
The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, it sends the next
byte. To stop the transmitter from sending the following byte, CTS must be released before the middle of the last
stop bit that is currently being sent (see Figure 1). The auto-CTS function reduces interrupts to the host system.
When flow control is enabled, CTS level changes do not trigger host interrupts because the device automatically
controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the transmit FIFO and
a receiver overrun error may result.
Auto-RTS data flow control originates in the receiver timing and control block (see functional block diagram) and
is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level of
1, 4, or 8 (see Figure 2), RTS is deasserted. With trigger levels of 1, 4, and 8, the sending ACE may send an
additional byte after the trigger level is reached (assuming the sending ACE has another byte to send) because
it may not recognize the deassertion of RTS until after it has begun sending the additional byte. RTS is
automatically reasserted once the RCV FIFO is emptied by reading the receiver buffer register.
When the trigger level is 14 (see Figure 3), RTS is deasserted after the first data bit of the 16th character is
present on the RX line. RTS is reasserted when the RCV FIFO has at least one available byte space.
Autoflow control is enabled by setting modem control register bits 5 (autoflow enable or AFE) and 1 (RTS) to a
1. Autoflow incorporates both auto-RTS and auto-CTS. When only auto-CTS is desired, bit 1 in the modem
control register should be cleared (this assumes that a control signal is driving CTS).
Figure 2. CTS Functional Timing Waveforms
6
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