MOTOROLA CMOS LOGIC DATA

3

MC14554B

Characteristic

Symbol

VDD

Min

Typ #

Max

Unit

Output Rise and Fall Time

tTLH, tTHL = (1.5 ns/pF) CL + 25 ns

tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns

tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns

tTLH,

tTHL

5.0

10

15

—

—

100

50

40

200

100

80

ns

Propagation Delay Time

K0 to C0

tPLH, tPHL = (1.7 ns/pF) CL + 185 ns

tPLH, tPHL = (0.66 ns/pF) CL + 82 ns

tPLH, tPHL = (0.5 ns/pF) CL + 60 ns

M0 to S2

tPLH, tPHL = (1.7 ns/pF) CL + 595 ns

tPLH, tPHL = (0.66 ns/pF) CL + 247 ns

tPLH, tPHL = (0.5 ns/pF) CL + 185 ns

tPLH,

tPHL

5.0

10

15

5.0

10

15

—

—

—

—

—

—

270

115

85

680

280

210

675

290

215

1700

750

570

ns

* The formulas given are for the typical characteristics only at 25

_C.

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Figure 1. Dynamic Power Dissipation

Waveforms

Figure 2. Dynamic Signal Waveforms

All outputs connected to respective

CL loads. f = system clock frequency

LOGIC DIAGRAM

MULTIPLIER CELL

Inputs X0, X1, Y0, Y1, K1, and M2 low, and inputs

M0 and M1 high.

MULTIPLIER

CELL

20 ns

20 ns

VDD

VSS

VOH

VOL

90%

50%

10%

2f

1

ALL INPUTS

(50% DUTY CYCLE)

ANY OUTPUT

(50% DUTY CYCLE)

VDD

VSS

VOH

VOL

20 ns

20 ns

90%

50%

10%

tPLH

tPHL

50%

90%

10%

tTLH

tTHL

OUTPUT

C0 OR S2

INPUT

K0 OR M0

M1

Y1

M0

Y0

4

5

M2

C0

X0

K0

14

12

3

2

1

15

M

Y

M

Y

X

X

K

K

S

C

S

C

MULTIPLIER

CELL

M

X

K

S

C

Y

M

X

K

S

C

Y

MULTIPLIER

CELL

MULTIPLIER

CELL

6

7

9

11

S2

S1

S0

C1(S3)

X1

K1

M

Y

X

K

L

S

C

For K0 to C0:

Inputs X1, Y1, and K0 low, and inputs X0, Y0,

K1, M1, and M2 high.

For M0 to S2:

13

10