KM62256CLP-7 datasheet(7/9 Pages) SAMSUNG

Teilenummer	KM62256CLP-7

Bauteilbeschribung	32Kx8 bit Low Power CMOS Static RAM

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Hersteller	SAMSUNG [Samsung semiconductor]

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7 / 9 page

Revision 4.0

KM62256C Family

CMOS SRAM

December 1997

7

TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)

Address

CS

tWC

tWR(4)

tAS(3)

tDW

tDH

Data Valid

WE

Data in

Data out

High-Z

tCW(2)

tWP(1)

tAW

NOTES (WRITE CYCLE)

1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE

going low : A write end at the earliest transition amongCS going high and WE going high, tWP is measured from the begining of write

to the end of write.

2. tCW is measured from the CS going low to end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.

DATA RETENTION WAVE FORM

CS controlled

VCC

4.5V

2.2V

VDR

CS

GND

Data Retention Mode

CS

≥VCC - 0.2V

tSDR

tRDR

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

Address

CS

tCW(2)

tWR(4)

tWP(1)

tDW

tDH

tOW

tWHZ

Data Undefined

Data Valid

WE

Data in

Data out

tWC

tAW

tAS(3)

Ähnliche Beschreibung - KM62256CLP-7

Hersteller	Teilenummer	Datenblatt	Bauteilbeschribung
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