KM681002A, KM681002AI

CMOS SRAM

PRELIMINARY

Rev 4.0

- 5 -

Ferruary 1998

WRITE CYCLE

NOTE : The above parameters are also guaranteed at industrial temperature range.

Parameter

Symbol

KM681002A-12

KM681002A-15

KM681002A-20

Unit

Min

Max

Min

Max

Min

Max

Write Cycle Time

12

-

15

-

20

-

ns

Chip Select to End of Write

8

-

10

-

12

-

ns

Address Set-up Time

0

-

0

-

0

-

ns

Address Valid to End of Write

8

-

10

-

12

-

ns

Write Pulse Width(OE High)

8

-

10

-

12

-

ns

Write Pulse Width(OE Low)

12

-

15

-

20

-

ns

Write Recovery Time

0

-

0

-

0

-

ns

Write to Output High-Z

0

6

0

7

0

9

ns

Data to Write Time Overlap

6

-

7

-

9

-

ns

Data Hold from Write Time

0

-

0

-

0

-

ns

End Write to Output Low-Z

3

-

3

-

3

-

ns

Address

Data Out

Previous Valid Data

Valid Data

TIMMING DIAGRAMS

CS

Address

OE

Data out

Valid Data

50%

50%

Current