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ISL12020MIRZ-T Datenblatt(PDF) 6 Page - Intersil Corporation

Teilenummer ISL12020MIRZ-T
Bauteilbeschribung  Low Power RTC with Battery Backed SRAM, Integrated 짹5ppm Temperature Compensation and Auto Daylight Saving
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Hersteller  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL12020MIRZ-T Datenblatt(HTML) 6 Page - Intersil Corporation

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6
FN6667.4
February 11, 2010
IRQ/FOUT (OPEN DRAIN OUTPUT)
VOL
Output Low Voltage
VDD = 5V, IOL = 3mA
0.4
V
VDD = 2.7V, IOL = 1mA
0.4
V
DC Operating Characteristics - RTC Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise
stated. Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
(Note 8)
TYP
(Note 9)
MAX
(Note 8) UNITS NOTES
Power-Down Timing Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise stated.
Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
(Note 8)
TYP
(Note 9)
MAX
(Note 8) UNITS
NOTES
VDDSR-
VDD Negative Slew rate
10
V/ms
14
I2C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise
specified. Boldface limits apply over the operating temperature range,
-40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 8)
TYP
(Note 9)
MAX
(Note 8) UNITS
NOTES
VIL
SDA and SCL Input Buffer
LOW Voltage
-0.3
0.3 x
VDD
V
VIH
SDA and SCL Input Buffer
HIGH Voltage
0.7 x VDD
VDD +
0.3
V
Hysteresis
SDA and SCL Input Buffer
Hysteresis
0.05 x VDD
V
15, 16
VOL
SDA Output Buffer LOW
Voltage, Sinking 3mA
VDD = 5V, IOL = 3mA
0
0.02
0.4
V
CPIN
SDA and SCL Pin Capacitance TA = +25°C, f = 1MHz,
VDD = 5V, VIN =0V,
VOUT = 0V
10
pF
15, 16
fSCL
SCL Frequency
400
kHz
tIN
Pulse Width Suppression
Time at SDA and SCL Inputs
Any pulse narrower than
the max spec is
suppressed.
50
ns
tAA
SCL Falling Edge to SDA
Output Data Valid
SCL falling edge
crossing 30% of VDD,
until SDA exits the 30%
to 70% of VDD window.
900
ns
tBUF
Time the Bus Must be Free
Before the Start of a New
Transmission
SDA crossing 70% of
VDD during a STOP
condition, to SDA
crossing 70% of VDD
during the following
START condition.
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of
VDD crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of
VDD crossing.
600
ns
tSU:STA
START Condition Setup Time SCL rising edge to SDA
falling edge. Both
crossing 70% of VDD.
600
ns
ISL12020M


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