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March 19, 2008

ISL54302 Detailed Description

The ISL54302 quad analog switches offer switching capability

from a split-supply -3V and +9V or single 0V and 5V to 12V

supply. Please review “Power Supply Considerations” on

page 7 before powering up the device.

The user can employ multi-device control data in two ways.

The S1-S4-CTRL lines can be connected to several devices,

with each device having its own CS-LATCH connection to

the system controller. The other way is to have separate

S1-4-CTRL connections for each switch and a single

CS-LATCH connection to all ISL54302s.

Power Supply Considerations

The ISL54302 construction consists of CMOS analog

switches and four supply pins: VPLUS, VSS, VLOGIC, VDD

and GND. VPLUS and VSS determine the switch voltage

range of the four SPST CMOS switches and set their analog

voltage limits. There are no connections between the switch

contact signal path and GND.

VLOGIC and GND power the digital input/output logic level

shifters (thus setting the digital switching point). The level

shifters convert the external logic levels to VDD and VSS

signals to drive the internal digital circuitry.

VDD and VSS power the internal logic of the device. VDD

must always be held at a fixed 3V above VSS to avoid

device damage.

Whether operating split or single device, GND will

always be @ 0V and VLOGIC will always be @ 3V.

VDD should always remain 3V above VSS. VSS to

VPLUS should not exceed a maximum spread of more

than 12V. For examples, see the following:

SPLIT POSITIVE AND NEGATIVE SWITCH RANGE

OPERATION

• VSS = -3V, VDD = +0V, VPLUS = +9V, VLOGIC = 3V

• VSS = -1V, VDD = +2V, VPLUS = +11V, VLOGIC = 3V

POSITIVE SWITCH RANGE OPERATION

• VSS = 0V, VDD = +3V, VPLUS = +12V, VLOGIC = 3V

ISL54302 Parallel Communications

The ISL54302 operates based on parallel data. CTRL and

LATCH inputs are 3V level compatible. Setup and Hold times

relative to the rising the edge of the CS-LATCH input must

be maintained for proper operation. Switch control data is

clocked into internal registers on the rising edge of

CS-LATCH.

MULTIPLE DEVICE CONNECTION

The user can configure the four SX-CTRL inputs to connect

to several ISL54302’s. In this configuration each ISL54302

requires a separate/dedicated CS-LATCH input. Therefore,

each device will update at different times.

So in essence, the S1-S4-CTRL signals are multiplexed and

connected to all switch control inputs in parallel (see Figure 8).

For non-multiplexed connections, each SX-CTRL input must

have a dedicated logic input for each switch/each device. If

three ISL54302s are being used, the user must supply 12

dedicated SX-CTRL signals. All switches are then tied to the

same CS-LATCH pin and all devices would change state at

the same time.

ISL54302 CS-LATCH Pin Discussion

The ISL54302’s operational state does not change while

SX-CTRL inputs are changing. The user must insure that the

CS-LATCH pin remains low and does not change state while

SX-CTRL inputs are changing.

Once the user has set the SX-CTRL inputs, the CS-LATCH

pin is then utilized. Just as the CS-LATCH pin must remain

low during SX-CTRL setup, the SX-CTRL pins must remain

stable during and after the CS-LATCH operation.

The switch from present to next operation occurs on the

rising edge on the CS-LATCH pin. This rising edge transfers

data to the internal 4-bit switch control registers. This

transfer updates opening/closing of the four switches.

ISL54302 Power On Reset (POR)

Switch conditions are controlled during POR (Power On

Reset). During and after a POR condition, the switches are

opened until closed by the controller.

FIGURE 5. SETUP AND HOLD TIMES

CS-LATCH

INPUT

SX-CTRL

DATA = 1

100%

100%

DATA = 0

SX-CTRL SHOULD REMAIN IN DESIRED STATE, BEFORE DURING AND AFTER CS-LATCH.

50%

50%

ISL54302