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BF1202 Datenblatt(PDF) 7 Page - NXP Semiconductors |
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BF1202 Datenblatt(HTML) 7 Page - NXP Semiconductors |
7 / 15 page 2010 Sep 16 7 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR handbook, halfpage 02 46 40 30 10 0 20 MCD960 VG2-S (V) IG1 ( μA) 4 V 3.5 V 3 V 4.5 V VGG = 5 V Fig.13 Gate 1 current as a function of gate 2 voltage; typical values. VDS =5 V; Tj =25 C. RG1 =120 k (connected to VGG); see Fig.21. handbook, halfpage 01 2 4 0 −50 −10 3 VAGC (V) gain reduction (dB) −20 −30 −40 MCD961 Fig.14 Typical gain reduction as a function of the AGC voltage; see Fig.21. VDS =5 V; VGG =5 V; RG1 = 120 k; f = 50 MHz; Tamb =25 C. handbook, halfpage 0 gain reduction (dB) 10 50 120 110 90 80 100 20 30 40 MCD962 Vunw (dB μV) Fig.15 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; Fig.21. VDS =5 V; VGG =5 V; RG1 = 120 k; f= 50 MHz; funw =60MHz; Tamb =25 C. handbook, halfpage 0 gain reduction (dB) 10 50 16 12 4 0 8 20 30 40 MCD963 ID (mA) Fig.16 Drain current as a function of gain reduction; typical values; see Fig.21. VDS =5 V; VGG =5 V; RG1 = 120 k; f = 50 MHz; Tamb =25 C. |
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