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TDA8023 Datenblatt(PDF) 7 Page - NXP Semiconductors |
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TDA8023 Datenblatt(HTML) 7 Page - NXP Semiconductors |
7 / 32 page TDA8023_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 16 July 2007 7 of 32 NXP Semiconductors TDA8023 Low power IC card interface 8.2.2 With external divider on pin PORADJ If an external resistor bridge is connected to pin PORADJ (R1 to GND and R2 to VDD as shown in Figure 1 and Figure 2), then the internal threshold voltages and the internal hysteresis voltage are overridden by externally determined ones. The voltage on pin PORADJ is: where The thresholds that are applied by the TDA8023 to this voltage VPORADJ are: (rising) (falling) where Vbg(int) = 1.25 V (typ) Vhys = 60 mV (typ) The thresholds and hysteresis on VDD can then be calculated from: (rising) (falling) The minimum threshold voltage Vth(POR)L should be chosen higher than 2 V. Input PORADJ is biased internally with a pull-down current source of 4 µA which is cut when the voltage on this pin exceeds 1 V. This ensures that after detection of the external bridge during power-on, the input current on this pin does not cause inaccuracy of the bridge voltage. 8.2.3 External capacitor on pin CDEL The width of the POR pulse (tW) is externally set by the value of the CDEL capacitor: the typical value is 1 ms per 2 nF. Usually CCDEL = 22 nF, therefore tW = 10 ms (typ). V PORADJ R1 R1 R2 + -------------------- V DD × kV DD × == k R1 R1 R2 + -------------------- = V th H () PORADJ () V bg int () V hys 2 ----------- + = V th L () PORADJ () V bg int () V hys 2 ----------- – = V th POR ()H V th H () PORADJ () k -------------------------------------- V bg int () V hys 2 ----------- + k ----------------------------------------- == V th POR ()L V th L () PORADJ () k ------------------------------------- V bg int () V hys 2 ----------- – k ----------------------------------------- == V hys POR () V hys k ----------- = |
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