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LC7455A Datenblatt(PDF) 3 Page - Sanyo Semicon Device |
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LC7455A Datenblatt(HTML) 3 Page - Sanyo Semicon Device |
3 / 13 page System Block Diagram No. 5680-3/13 LC7455A, 7455M Operation in the Different Modes Pin Application Mode equipment Operation MOD1 MOD0 · Even field line 21 data extraction Open Open Mode 1 VCR The internal PLL is operated with the horizontal synchronizing signal separated from the composite video signal as the reference. · Even field line 21 data extraction Open VDD Mode 2 VCR An external 508 kHz ceramic oscillator is used, and the internal PLL is operated with that oscillator output divided by 32 as the reference. VDD Open Mode 3 NTSC-TV · Odd and even field line 21 data extraction The internal PLL is operated with the Hsync signal applied from fly back as the reference. VDD VDD Mode 4 PAL-TV · Odd and even field line 22 data extraction The internal PLL is operated with the Hsync signal applied from the fly back circuit as the reference. Note: The data extraction operations in modes 1 and 2 are identical. However, while mode 1 can operate without problem for normal "on air" signals, it may be difficult for the PLL to lock with signals such as scrambled CATV signals. PLL reference clock mode 2 mode 3, 4 mode 1 Data peak hold (Data slice) Hsync peak hold (Hsync slice) Output control Data output buffer Divided-by- 32 circuit Oscillator circuit Pedestal clamp (Mode 2) (Mode 2) (Modes 1, 3, 4) |
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Ähnliche Beschreibung - LC7455A |
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