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LS7766 Datenblatt(PDF) 3 Page - LSI Computer Systems

Teilenummer LS7766
Bauteilbeschribung  32-BIT SINGLE- AXIS/DUAL-AXIS QUADRATURE COUNTER
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REGISTER DESCRIPTION:
Following is a list of the hardware registers for the
single-axis device. For the dual axis device, these
registers are duplicated for the second axis.
IDR
The IDR is a 32-bit data register directly address-
able for write. In the octal bus-configuration, the input
data is written in byte segments of byte0 (IDR0), byte1
(IDR1), byte2 (IDR2) and byte3 (IDR3). In the hex bus-
configuration the data is written in word segments of
word0 (IDR1:IDR0) and word1 (IDR3:IDR20).
B31------------------------------------------------------------------- B0
IDR:
IDR3
IDR2
IDR1
IDR0
B7------------B0 B7-----------B0 B7-----------B0 B7---------B0
-----byte3------ -----byte2----- -----byte1----- -----byte0-----
--------------- word1---------------- --------------- word0 ------------
The IDR serves as the input portal for the counter
(CNTR) since the CNTR is not directly addressable for
either read or write. In order to preset the CNTR to any
desired value the data is first written into the IDR and
then transferred to the CNTR.
In
mod-n and range-limit count modes the IDR serves
as the repository for the division factor n and the count
range-limit, respectively. The IDR can also be used to
hold a target position data for comparing with the
running CNTR. A compare equality flag is generated at
IDR = CNTR to signal the event of arriving at the target.
CNTR:
The CNTR is a 32-bit up/down counter which counts the
up/down pulses resulting from the quadrature clocks
applied at A and B inputs or alternatively, in non-
quadrature mode, pulses applied at the A input. The
CNTR is not directly accessible for read or write; instead
it can be preloaded with data from the IDR or it can port
its own data out to the ODR which in turn can be ac-
cessed by read operation. In both quadrature and non-
quadrature modes, the CNTR can be further configured
into either free-running or single-cycle or mod-n or
range-limit mode. In quadrature mode, the count
resolution is programmable to be x1 or x2 or x4 of the
A quad B cycles.
ODR:
The ODR is a 32-bit data register directly addressable
for read. In the octal bus-configuration, the output data is
read in byte segments of byte0 (ODR0), byte1 (ODR1),
byte2 (ODR2), and byte3 (ODR3). In the hex bus-
configuration the data is read in word segments of word0
(ODR1:ODR0) and word1 (ODR3:ODR2).
B31------------------------------------------------------------------- B0
ODR:
ODR3
ODR2
ODR1
ODR0
B7------------B0 B7-----------B0 B7-----------B0 B7---------B0
-----byte3------ -----byte2----- -----byte1----- -----byte0-----
--------------- word1---------------- --------------- word0 ------------
STR:
The STR is an 8-bit status register indicating count related
status.
STR:
CY BW CMP IDX CEN 0 U/D S
B7 B6
B5 B4 B3 B2 B1 B0
An individual STR bit is set to 1 when the bit related event
has taken place. The STR is cleared to 0 at power-up. The
STR can also be cleared through the control register TCR
with the exception of bit_1(U/D) and bit3_(CEN). These two
STR bits always indicate the instantaneous status of the
count_direction and count_enable assertion/de-assertion.
The STR bits are described below:
B7 (CY): Carry; set by CNTR overflow
B6 (BW): Borrow; set by CNTR underflow
B5 (CMP): Set when CNTR = PR
B4 (IDX): Set when INDX input is at active level
B3 (CEN): Set when counting is enabled,
reset when counting is disabled
B2 (0):
Always 0
B1 (U/D): Set when counting up,
reset when counting down
B0 (S):
Sign of count value;
set when negative, reset when positive
7766-042407-3
TCR:
The TCR is a write only register, which when written into, gener-
ates transient signals to perform load and reset operations as
described below:
TCR: B7 B6 B5 B4 B3 B2 B1 B0
B0 = 0: Nop
= 1: Reset CNTR to 0.
(Should not be combined with
load_CNTR operation).
B1 = 0: Nop
= 1: Load CNTR from IDR. Affects all 32 bits.
(Should not be combined with
reset_CNTR operation)
B2 = 0: Nop
= 1: Load ODR from CNTR. Affects all 32 bits.
B3 = 0: Nop
= 1: Reset STR.
Affects status bits for carry, borrow, compare and
index. Status bits corresponding to count_enable,
count direction and sign are not affected
B4 = 0: Nop.
1: Master reset. Resets MCR0, MCR1, IDR, ODR, STR
B5 = 0: Nop
1: Set sign bit (STR bit0)
B6 = 0: Nop
1: Reset sign bit (STR bit0)
B7 = x: Not used.


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