CD System Block Diagrams

Pin Applications

An EFM signal (NRZ) sliced at an optimal level can be acquired

by inputting the HF signal to EFMIN.

The LC78620E handles defects as follows. When a high level is

input to the DEFI pin (pin 1), the EFMO (pin 9) and EFMO (pin

10) pins (the slice level control outputs) go to the high-

impedance state, and the slice level is held. However, note that

this function is only valid in CLV phase control mode, that is,

when the V/P pin (pin 15) is low. This function can be used in

combination with the LA9230M and LA9231M DEF pins.

other, unwanted radiation can result in error rate

shield line between these two lines.

2. PLL Clock Generation Circuit; Pin 3: PDO, pin 5: ISET, pin 7: FR, pin 21: PCK

Since the LC78620E includes a VCO circuit, a PLL circuit can

be formed by connecting an external RC circuit. ISET is the

charge pump reference current, PDO is the VCO circuit loop

filter, and FR is a resistor that determines the VCO frequency

range.

(Reference values)

R1 = 68 k

Ω, C1 = 0.1 µF

R2 = 680 k

Ω, C2 = 0.1 µF

R3 = 5.1 k

Ω

Note: We recommend using a ±1.0% tolerance (rank F) carbon

firm resistor for R3.

3. VCO Monitor; Pin 21: PCK

PCK is a monitor pin that outputs an average frequency of 4.3218 MHz, which is divided from the VCO frequency.

4. Synchronization Detection Monitor; Pin 22: FSEQ

Pin 22 goes high when the frame synchronization (a positive polarity synchronization signal) from the EFM signal

read in by PCK and the timing generated by the counter (the interpolation synchronization signal) agree. This pin is

thus a synchronization detection monitor. (It is held high for a single frame.)

No. 5130-9/34

LC78620E