No. 4909-8/13

LC8220

Code Bus Write Cycle

Code Bus Write Cycle (type 1)

Code Bus Write Cycle (type 2)

Item

Minimum

Maximum

Unit

t1

Write signal assert setup time (referenced to CLK)

8

ns

t2

Write signal assert hold time (referenced to CLK)

15

ns

t3

Chip select stabilization time (referenced to the write signal)

0

ns

t4

Chip select hold time (referenced to the write signal)

0

ns

t5

Write cycle selection signal stabilization time (referenced to the write signal)

0

ns

t6

Write cycle selection signal hold time (referenced to the write signal)

0

ns

t7

Ready signal response delay time (referenced to the write signal)

T + t1 + 20

ns

t8

Ready signal release delay time (referenced to the write signal)

t9 + 27

ns

t9

Write signal negate setup time (referenced to CLK)

8

ns

t10

Write signal negate hold time (referenced to CLK)

15

ns

t11

Data setup time (referenced to the ready signal)

45

ns

t12

Data hold time (referenced to the ready signal)

15

ns

T

Clock period

60

ns