STK22C48

Document Number: 001-51000 Rev. *D

Page 3 of 17

Pin Configurations

Figure 1. Pin Diagram - 28-pin SOIC

Table 1. Pin Definitions

Pin Name

Alt

IO Type

Description

Input

Address inputs. Used to select one of the 2,048 bytes of the nvSRAM.

Input or output Bidirectional data IO lines. Used as input or output lines depending on operation.

WE

W

Input

Write enable input, active LOW. When the chip is enabled and WE is LOW, data on the IO

pins is written to the specific address location.

CE

E

Input

Chip enable input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip.

OE

G

Input

Output enable, active LOW. The active LOW OE input enables the data output buffers during

read cycles. Deasserting OE HIGH causes the IO pins to tri-state.

Ground

Ground for the device. The device is connected to ground of the system.

Power supply Power supply inputs to the device.

HSB

Input or output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress.

When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal

pull-up resistor keeps this pin high if not connected (connection optional).

Power supply AutoStore capacitor. Supplies power to nvSRAM during power loss to store data from SRAM

to nonvolatile elements.

NC

No connect

No connect. This pin is not connected to the die.

HSB

WE

OE

DQ6

DQ7

DQ5

CE

DQ4

DQ3

1

2

3

4

5

6

7

8

9

10

11

12

13

14

DQ0

DQ1

DQ2

28-SOIC

Top View

(Not To Scale)

NC

NC

28

27

26

25

24

23

22

21

20

19

18

17

16

15

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