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FAN2106 Datenblatt(PDF) 10 Page - Fairchild Semiconductor |
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FAN2106 Datenblatt(HTML) 10 Page - Fairchild Semiconductor |
10 / 15 page © 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN2106 • Rev. 1.1.0 10 Circuit Description PWM Generation Refer to Figure 2 for the PWM control mechanism. FAN2106 uses the summing-mode method of control to generate the PWM pulses. An amplified current-sense signal is summed with an internally generated ramp and the combined signal is compared with the output of the error amplifier to generate the pulsewidth to drive the high-side MOSFET. Sensed current from the previous cycle is used to modulate the output of the summing block. The output of the summing block is also compared against a voltage threshold set by the RLIM resistor to limit the inductor current on a cycle-by-cycle basis. The RRAMP resistor helps set the charging current for the internal ramp and provides input voltage feed- forward function. The controller facilitates external compensation for enhanced flexibility. Initialization Once VCC exceeds the UVLO threshold and EN is HIGH, the IC checks for a shorted FB pin before releasing the internal soft-start ramp (SS). If the parallel combination of R1 and RBIAS is ≤ 1KΩ, the internal SS ramp is not released and the regulator does not start. Enable FAN2106 has an internal pull-up to the ENABLE (EN) pin so that the IC is enabled once VCC exceeds the UVLO threshold. Connecting a small capacitor across EN and AGND delays the rate of voltage rise on the EN pin. The EN pin also serves for the restart whenever a fault occurs (refer to the Auto-Restart section). If the regulator is enabled externally, the external EN signal should go HIGH only after VCC is established. For applications where such sequencing is required, FAN2106 can be enabled (after the VCC comes up) with external control, as shown in Figure 21. 14 FAN2106 EN 3.3n Figure 21. Enabling with External Control Soft-Start Once internal SS ramp has charged to 0.8V (T0.8), the output voltage is in regulation. Until SS ramp reaches 1.0V (T1.0), the fault latch is inhibited. To avoid skipping the soft-start cycle, it is necessary to apply VIN before VCC reaches its UVLO threshold. Normal sequence for powering up would be VIN VCC EN. Soft-start time is a function of switching frequency. SS 1.35V FB EN 0.8V T0.8 T1.0 3200 CLKs 4000 CLKs Fault Latch Enable 0.8V 1.0V 2400 CLKs Figure 22. Soft-Start Timing Diagram Cycling VCC or the EN pin discharges the internal SS and resets the IC. In applications where external EN signal is used, VIN and VCC should be established before the EN signal comes up to prevent skipping the soft-start function. Startup on Pre-Bias The regulator does not allow the low-side MOSFET to operate in full synchronous rectification mode until internal SS ramp reaches 95% of VREF (~0.76V). This helps the regulator start on a pre-biased output and ensures that the pre-biased outputs are not discharged during soft-start. Protections The converter output is monitored and protected against extreme overload, short-circuit, over-voltage, under-voltage, and over-temperature conditions. Under-Voltage Shutdown If the voltage on the FB pin remains below the under- voltage threshold for 16 consecutive clock cycles, the fault latch is set and the converter shuts down. This protection is not active until the internal SS ramp reaches 1.0V during soft-start. Over-Voltage Protection If voltage on the FB pin exceeds 115% of VREF for two consecutive clock cycles, the fault latch is set and shutdown occurs. A shorted high-side MOSFET condition is detected when SW voltage exceeds ~0.7V while the low-side |
Ähnliche Teilenummer - FAN2106_09 |
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Ähnliche Beschreibung - FAN2106_09 |
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